1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sbc8349.c -- WindRiver SBC8349 board support.
4 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 *
6 * Paul Gortmaker <paul.gortmaker@windriver.com>
7 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 */
9
10 #include <common.h>
11 #include <ioports.h>
12 #include <mpc83xx.h>
13 #include <asm/mpc8349_pci.h>
14 #include <i2c.h>
15 #include <spd_sdram.h>
16 #include <miiphy.h>
17 #if defined(CONFIG_OF_LIBFDT)
18 #include <linux/libfdt.h>
19 #endif
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 int fixed_sdram(void);
24 void sdram_init(void);
25
26 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
27 void ddr_enable_ecc(unsigned int dram_size);
28 #endif
29
30 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)31 int board_early_init_f (void)
32 {
33 return 0;
34 }
35 #endif
36
37 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
38
dram_init(void)39 int dram_init(void)
40 {
41 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
42 u32 msize = 0;
43
44 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
45 return -1;
46
47 /* DDR SDRAM - Main SODIMM */
48 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
49 #if defined(CONFIG_SPD_EEPROM)
50 msize = spd_sdram();
51 #else
52 msize = fixed_sdram();
53 #endif
54 /*
55 * Initialize SDRAM if it is on local bus.
56 */
57 sdram_init();
58
59 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
60 /*
61 * Initialize and enable DDR ECC.
62 */
63 ddr_enable_ecc(msize * 1024 * 1024);
64 #endif
65 /* set total bus SDRAM size(bytes) -- DDR */
66 gd->ram_size = msize * 1024 * 1024;
67
68 return 0;
69 }
70
71 #if !defined(CONFIG_SPD_EEPROM)
72 /*************************************************************************
73 * fixed sdram init -- doesn't use serial presence detect.
74 ************************************************************************/
fixed_sdram(void)75 int fixed_sdram(void)
76 {
77 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
78 u32 msize = CONFIG_SYS_DDR_SIZE;
79 u32 ddr_size = msize << 20; /* DDR size in bytes */
80 u32 ddr_size_log2 = __ilog2(msize);
81
82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
83 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
84
85 #if (CONFIG_SYS_DDR_SIZE != 256)
86 #warning Currently any ddr size other than 256 is not supported
87 #endif
88
89 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
90 #warning Chip select bounds is only configurable in 16MB increments
91 #endif
92 im->ddr.csbnds[2].csbnds =
93 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
94 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
95 CSBNDS_EA_SHIFT) & CSBNDS_EA);
96 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
97
98 /* currently we use only one CS, so disable the other banks */
99 im->ddr.cs_config[0] = 0;
100 im->ddr.cs_config[1] = 0;
101 im->ddr.cs_config[3] = 0;
102
103 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
104 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
105
106 im->ddr.sdram_cfg =
107 SDRAM_CFG_SREN
108 #if defined(CONFIG_DDR_2T_TIMING)
109 | SDRAM_CFG_2T_EN
110 #endif
111 | SDRAM_CFG_SDRAM_TYPE_DDR1;
112 #if defined (CONFIG_DDR_32BIT)
113 /* for 32-bit mode burst length is 8 */
114 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
115 #endif
116 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
117
118 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
119 udelay(200);
120
121 /* enable DDR controller */
122 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
123 return msize;
124 }
125 #endif/*!CONFIG_SYS_SPD_EEPROM*/
126
127
checkboard(void)128 int checkboard (void)
129 {
130 puts("Board: Wind River SBC834x\n");
131 return 0;
132 }
133
134 /*
135 * if board is fitted with SDRAM
136 */
137 #if defined(CONFIG_SYS_BR2_PRELIM) \
138 && defined(CONFIG_SYS_OR2_PRELIM) \
139 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
140 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
141 /*
142 * Initialize SDRAM memory on the Local Bus.
143 */
144
sdram_init(void)145 void sdram_init(void)
146 {
147 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
148 volatile fsl_lbc_t *lbc = &immap->im_lbc;
149 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
150 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
151 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
152 LSDMR_WRC3 | LSDMR_CL3;
153
154 puts("\n SDRAM on Local Bus: ");
155 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
156
157 /*
158 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
159 */
160
161 /* setup mtrpt, lsrt and lbcr for LB bus */
162 lbc->lbcr = 0x00000000;
163 /* LB refresh timer prescal, 266MHz/32 */
164 lbc->mrtpr = 0x20000000;
165 /* LB sdram refresh timer, about 6us */
166 lbc->lsrt = 0x32000000;
167 asm("sync");
168
169 /*
170 * Configure the SDRAM controller Machine Mode Register.
171 */
172 /* 0x40636733; normal operation */
173 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
174
175 /* 0x68636733; precharge all the banks */
176 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
177 asm("sync");
178 *sdram_addr = 0xff;
179 udelay(100);
180
181 /* 0x48636733; auto refresh */
182 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
183 asm("sync");
184 /*1 times*/
185 *sdram_addr = 0xff;
186 udelay(100);
187 /*2 times*/
188 *sdram_addr = 0xff;
189 udelay(100);
190 /*3 times*/
191 *sdram_addr = 0xff;
192 udelay(100);
193 /*4 times*/
194 *sdram_addr = 0xff;
195 udelay(100);
196 /*5 times*/
197 *sdram_addr = 0xff;
198 udelay(100);
199 /*6 times*/
200 *sdram_addr = 0xff;
201 udelay(100);
202 /*7 times*/
203 *sdram_addr = 0xff;
204 udelay(100);
205 /*8 times*/
206 *sdram_addr = 0xff;
207 udelay(100);
208
209 /* 0x58636733; mode register write operation */
210 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
211 asm("sync");
212 *sdram_addr = 0xff;
213 udelay(100);
214
215 /* 0x40636733; normal operation */
216 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
217 asm("sync");
218 *sdram_addr = 0xff;
219 udelay(100);
220 }
221 #else
sdram_init(void)222 void sdram_init(void)
223 {
224 puts(" SDRAM on Local Bus: Disabled in config\n");
225 }
226 #endif
227
228 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)229 int ft_board_setup(void *blob, bd_t *bd)
230 {
231 ft_cpu_setup(blob, bd);
232 #ifdef CONFIG_PCI
233 ft_pci_setup(blob, bd);
234 #endif
235
236 return 0;
237 }
238 #endif
239