1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2013 Seco USA Inc 4 * 5 * Refer doc/README.imximage for more details about how-to configure 6 * and create imximage boot image 7 * 8 * The syntax is taken as close as possible with the kwbimage 9 */ 10 11/* image version */ 12IMAGE_VERSION 2 13 14/* 15 * Boot Device : one of 16 * spi, sd (the board has no nand neither onenand) 17 */ 18BOOT_FROM sd 19 20#define __ASSEMBLY__ 21#include <config.h> 22#include "asm/arch/mx6-ddr.h" 23#include "asm/arch/iomux.h" 24#include "asm/arch/crm_regs.h" 25 26/* DDR IO TYPE */ 27DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 28DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 29 30/* DATA STROBE */ 31DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 32DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 33DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 34DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 35DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 36DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 37DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 38DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 39DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 40 41/* DATA */ 42DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 43DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 44DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 45DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 46DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 47DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 48DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 49DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 50DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 51DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 52DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 53DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 54DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 55DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 56DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 57DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 58DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 59/* ADDRESS */ 60DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028 61DATA 4, MX6_IOM_DRAM_CAS, 0x00000028 62DATA 4, MX6_IOM_DRAM_RAS, 0x00000028 63 64/* CONTROL */ 65DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 66DATA 4, MX6_IOM_DRAM_RESET, 0x00000028 67DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 68DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028 69DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028 70 71/* CLOCK */ 72DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 73DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 74 75/* 76 * DDR3 SETTINGS 77 * Read Data Bit Delay 78 */ 79DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 80DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 81DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 82DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 83DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 84DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 85DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 86DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 87 88 89/* Write Leveling */ 90DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 91DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 92DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001 93DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 94 95/* DQS gating, read delay, write delay calibration values */ 96DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326 97DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B 98DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340 99DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C 100 101/* Read calibration */ 102DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137 103DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45 104 105/* write calibration */ 106DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741 107DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C 108 109/* Complete calibration by forced measurement: */ 110DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 111DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 112 113/* 114 * MMDC init: 115 * in DDR3, 64-bit mode, only MMDC0 is init 116 */ 117DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 118DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 119 120DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955 121DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 122DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 123 124DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 125DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 126DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 127DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 128 129/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */ 130DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 131 132/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */ 133DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 134 135/* Initialize DDR3 on CS_0 and CS_1 */ 136DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032 137DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 138DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 139 140/* P0 01c */ 141/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */ 142DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 143 144/*ZQ - Calibrationi */ 145DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 146DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 147DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 148 149DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 150DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 151 152DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 153 154DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 155DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 156 157/* set the default clock gate to save power */ 158DATA 4, CCM_CCGR0, 0x00C03F3F 159DATA 4, CCM_CCGR1, 0x0030FC03 160DATA 4, CCM_CCGR2, 0x0FFFC000 161DATA 4, CCM_CCGR3, 0x3FF00000 162DATA 4, CCM_CCGR4, 0x00FFF300 163DATA 4, CCM_CCGR5, 0x0F0000C3 164DATA 4, CCM_CCGR6, 0x000003FF 165 166/* enable AXI cache for VDOA/VPU/IPU */ 167DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF 168 169/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 170DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 171DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 172 173