1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Technexion Ltd.
4 *
5 * Author: Richard Hu <richard.hu@technexion.com>
6 * Fabio Estevam <festevam@gmail.com>
7 */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <linux/errno.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/video.h>
17 #include <mmc.h>
18 #include <fsl_esdhc_imx.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/io.h>
21 #include <asm/arch/sys_proto.h>
22 #include <spl.h>
23
24 #if defined(CONFIG_SPL_BUILD)
25 #include <asm/arch/mx6-ddr.h>
26
27 #define IMX6DQ_DRIVE_STRENGTH 0x30
28 #define IMX6SDL_DRIVE_STRENGTH 0x28
29
30 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)31 int spl_start_uboot(void)
32 {
33 /* Break into full U-Boot on 'c' */
34 if (serial_tstc() && serial_getc() == 'c')
35 return 1;
36
37 return 0;
38 }
39 #endif
40
41 /* configure MX6Q/DUAL mmdc DDR io registers */
42 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
43 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
44 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
45 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
46 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
47 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
48 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
49 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
50 .dram_sdba2 = 0x00000000,
51 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
52 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
53 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
54 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
55 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
56 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
57 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
58 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
59 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
60 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
61 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
62 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
63 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
64 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
65 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
66 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
67 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
68 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
69 };
70
71 /* configure MX6Q/DUAL mmdc GRP io registers */
72 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
73 .grp_ddr_type = 0x000c0000,
74 .grp_ddrmode_ctl = 0x00020000,
75 .grp_ddrpke = 0x00000000,
76 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
77 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
78 .grp_ddrmode = 0x00020000,
79 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
80 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
81 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
82 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
83 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
84 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
85 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
86 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
87 };
88
89 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
90 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
91 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
92 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
93 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
94 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
95 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
96 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
97 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
98 .dram_sdba2 = 0x00000000,
99 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
100 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
101 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
102 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
103 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
104 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
105 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
106 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
107 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
108 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
109 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
110 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
111 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
112 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
113 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
114 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
115 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
116 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
117 };
118
119 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
120 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
121 .grp_ddr_type = 0x000c0000,
122 .grp_ddrmode_ctl = 0x00020000,
123 .grp_ddrpke = 0x00000000,
124 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
125 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
126 .grp_ddrmode = 0x00020000,
127 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
128 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
129 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
130 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
131 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
132 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
133 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
134 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
135 };
136
137 /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
138 static struct mx6_ddr3_cfg h5t04g63afr = {
139 .mem_speed = 800,
140 .density = 4,
141 .width = 16,
142 .banks = 8,
143 .rowaddr = 15,
144 .coladdr = 10,
145 .pagesz = 2,
146 .trcd = 1500,
147 .trcmin = 5250,
148 .trasmin = 3750,
149 };
150
151 /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
152 static struct mx6_ddr3_cfg h5tq2g63ffr = {
153 .mem_speed = 800,
154 .density = 2,
155 .width = 16,
156 .banks = 8,
157 .rowaddr = 14,
158 .coladdr = 10,
159 .pagesz = 2,
160 .trcd = 1500,
161 .trcmin = 5250,
162 .trasmin = 3750,
163 };
164
165 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
166 .p0_mpwldectrl0 = 0x00000000,
167 .p0_mpwldectrl1 = 0x00000000,
168 .p1_mpwldectrl0 = 0x00000000,
169 .p1_mpwldectrl1 = 0x00000000,
170 .p0_mpdgctrl0 = 0x032C0340,
171 .p0_mpdgctrl1 = 0x03300324,
172 .p1_mpdgctrl0 = 0x032C0338,
173 .p1_mpdgctrl1 = 0x03300274,
174 .p0_mprddlctl = 0x423A383E,
175 .p1_mprddlctl = 0x3638323E,
176 .p0_mpwrdlctl = 0x363C4640,
177 .p1_mpwrdlctl = 0x4034423C,
178 };
179
180 /* DDR 32bit */
181 static struct mx6_ddr_sysinfo mem_s = {
182 .dsize = 1,
183 .cs1_mirror = 0,
184 /* config for full 4GB range so that get_mem_size() works */
185 .cs_density = 32,
186 .ncs = 1,
187 .bi_on = 1,
188 .rtt_nom = 1,
189 .rtt_wr = 0,
190 .ralat = 5,
191 .walat = 0,
192 .mif3_mode = 3,
193 .rst_to_cke = 0x23,
194 .sde_to_rst = 0x10,
195 };
196
197 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
198 .p0_mpwldectrl0 = 0x001f001f,
199 .p0_mpwldectrl1 = 0x001f001f,
200 .p1_mpwldectrl0 = 0x001f001f,
201 .p1_mpwldectrl1 = 0x001f001f,
202 .p0_mpdgctrl0 = 0x420e020e,
203 .p0_mpdgctrl1 = 0x02000200,
204 .p1_mpdgctrl0 = 0x42020202,
205 .p1_mpdgctrl1 = 0x01720172,
206 .p0_mprddlctl = 0x494c4f4c,
207 .p1_mprddlctl = 0x4a4c4c49,
208 .p0_mpwrdlctl = 0x3f3f3133,
209 .p1_mpwrdlctl = 0x39373f2e,
210 };
211
212 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
213 .p0_mpwldectrl0 = 0x0040003c,
214 .p0_mpwldectrl1 = 0x0032003e,
215 .p0_mpdgctrl0 = 0x42350231,
216 .p0_mpdgctrl1 = 0x021a0218,
217 .p0_mprddlctl = 0x4b4b4e49,
218 .p0_mpwrdlctl = 0x3f3f3035,
219 };
220
ccgr_init(void)221 static void ccgr_init(void)
222 {
223 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
224
225 writel(0x00C03F3F, &ccm->CCGR0);
226 writel(0x0030FC03, &ccm->CCGR1);
227 writel(0x0FFFC000, &ccm->CCGR2);
228 writel(0x3FF03000, &ccm->CCGR3);
229 writel(0x00FFF300, &ccm->CCGR4);
230 writel(0x0F0000C3, &ccm->CCGR5);
231 writel(0x000003FF, &ccm->CCGR6);
232 }
233
spl_dram_init(void)234 static void spl_dram_init(void)
235 {
236 if (is_mx6solo()) {
237 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
238 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
239 } else if (is_mx6dl()) {
240 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
241 mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
242 } else if (is_mx6dq()) {
243 mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
244 mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
245 }
246
247 udelay(100);
248 }
249
board_init_f(ulong dummy)250 void board_init_f(ulong dummy)
251 {
252 ccgr_init();
253
254 /* setup AIPS and disable watchdog */
255 arch_cpu_init();
256
257 gpr_init();
258
259 /* iomux */
260 board_early_init_f();
261
262 /* setup GP timer */
263 timer_init();
264
265 /* UART clocks enabled and gd valid - init serial console */
266 preloader_console_init();
267
268 /* DDR initialization */
269 spl_dram_init();
270 }
271
272 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
273 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
274 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
275
276 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
277 {USDHC3_BASE_ADDR},
278 };
279
280 static iomux_v3_cfg_t const usdhc3_pads[] = {
281 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
282 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
283 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
284 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
285 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
286 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
287 /* SOM MicroSD Card Detect */
288 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
289 };
290
board_mmc_getcd(struct mmc * mmc)291 int board_mmc_getcd(struct mmc *mmc)
292 {
293 return 1;
294 }
295
board_mmc_init(bd_t * bis)296 int board_mmc_init(bd_t *bis)
297 {
298 SETUP_IOMUX_PADS(usdhc3_pads);
299 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
300 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
301 }
302 #endif
303
304 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)305 int board_fit_config_name_match(const char *name)
306 {
307 if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
308 return 0;
309 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
310 return 0;
311
312 return -EINVAL;
313 }
314 #endif
315