1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <asm/arch/clock.h>
4 #include <asm/arch/iomux.h>
5 #include <asm/arch/imx-regs.h>
6 #include <asm/arch/crm_regs.h>
7 #include <asm/arch/mx6ul_pins.h>
8 #include <asm/arch/mx6-pins.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/gpio.h>
11 #include <asm/mach-imx/iomux-v3.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <fsl_esdhc_imx.h>
14 #include <linux/libfdt.h>
15 #include <spl.h>
16
17 #if defined(CONFIG_SPL_BUILD)
18
19 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)20 int spl_start_uboot(void)
21 {
22 /* Break into full U-Boot on 'c' */
23 if (serial_tstc() && serial_getc() == 'c')
24 return 1;
25
26 return 0;
27 }
28 #endif
29
30 #include <asm/arch/mx6-ddr.h>
31
32 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
33 .grp_addds = 0x00000030,
34 .grp_ddrmode_ctl = 0x00020000,
35 .grp_b0ds = 0x00000030,
36 .grp_ctlds = 0x00000030,
37 .grp_b1ds = 0x00000030,
38 .grp_ddrpke = 0x00000000,
39 .grp_ddrmode = 0x00020000,
40 .grp_ddr_type = 0x00080000,
41 };
42
43 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
44 .dram_dqm0 = 0x00000030,
45 .dram_dqm1 = 0x00000030,
46 .dram_ras = 0x00000030,
47 .dram_cas = 0x00000030,
48 .dram_odt0 = 0x00000030,
49 .dram_odt1 = 0x00000030,
50 .dram_sdba2 = 0x00000000,
51 .dram_sdclk_0 = 0x00000030,
52 .dram_sdqs0 = 0x00000030,
53 .dram_sdqs1 = 0x00000030,
54 .dram_reset = 0x00000030,
55 };
56
57 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
58 .p0_mpwldectrl0 = 0x00000000,
59 .p0_mpdgctrl0 = 0x01380134,
60 .p0_mprddlctl = 0x40404244,
61 .p0_mpwrdlctl = 0x40405050,
62 };
63
64 static struct mx6_ddr_sysinfo ddr_sysinfo = {
65 .dsize = 0,
66 .cs1_mirror = 0,
67 .cs_density = 32,
68 .ncs = 1,
69 .bi_on = 1,
70 .rtt_nom = 1,
71 .rtt_wr = 0,
72 .ralat = 5,
73 .walat = 0,
74 .mif3_mode = 3,
75 .rst_to_cke = 0x23,
76 .sde_to_rst = 0x10,
77 .refsel = 1,
78 .refr = 3,
79 };
80
81 static struct mx6_ddr3_cfg mem_ddr = {
82 .mem_speed = 1333,
83 .density = 2,
84 .width = 16,
85 .banks = 8,
86 .coladdr = 10,
87 .pagesz = 2,
88 .trcd = 1350,
89 .trcmin = 4950,
90 .trasmin = 3600,
91 };
92
ccgr_init(void)93 static void ccgr_init(void)
94 {
95 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
96
97 writel(0xFFFFFFFF, &ccm->CCGR0);
98 writel(0xFFFFFFFF, &ccm->CCGR1);
99 writel(0xFFFFFFFF, &ccm->CCGR2);
100 writel(0xFFFFFFFF, &ccm->CCGR3);
101 writel(0xFFFFFFFF, &ccm->CCGR4);
102 writel(0xFFFFFFFF, &ccm->CCGR5);
103 writel(0xFFFFFFFF, &ccm->CCGR6);
104 }
105
imx6ul_spl_dram_cfg_size(u32 ram_size)106 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
107 {
108 if (ram_size == SZ_256M)
109 mem_ddr.rowaddr = 14;
110 else
111 mem_ddr.rowaddr = 15;
112
113 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
114 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
115 }
116
imx6ul_spl_dram_cfg(void)117 static void imx6ul_spl_dram_cfg(void)
118 {
119 ulong ram_size_test, ram_size = 0;
120
121 for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
122 imx6ul_spl_dram_cfg_size(ram_size);
123 ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
124 if (ram_size_test == ram_size)
125 break;
126 }
127
128 if (ram_size < SZ_256M) {
129 puts("ERROR: DRAM size detection failed\n");
130 hang();
131 }
132 }
133
board_init_f(ulong dummy)134 void board_init_f(ulong dummy)
135 {
136 ccgr_init();
137 arch_cpu_init();
138 board_early_init_f();
139 timer_init();
140 preloader_console_init();
141 imx6ul_spl_dram_cfg();
142 memset(__bss_start, 0, __bss_end - __bss_start);
143 board_init_r(NULL, 0);
144 }
145
reset_cpu(ulong addr)146 void reset_cpu(ulong addr)
147 {
148 }
149
150 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
151 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
152 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
153
154 static iomux_v3_cfg_t const usdhc1_pads[] = {
155 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 };
166
167 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
168 {USDHC1_BASE_ADDR},
169 };
170
board_mmc_getcd(struct mmc * mmc)171 int board_mmc_getcd(struct mmc *mmc)
172 {
173 return 1;
174 }
175
board_mmc_init(bd_t * bis)176 int board_mmc_init(bd_t *bis)
177 {
178 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
180 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
181 }
182 #endif
183