1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Technexion Ltd.
4 *
5 * Author: Richard Hu <richard.hu@technexion.com>
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx7-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch-mx7/mx7-ddr.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/gpio.h>
16 #include <fsl_esdhc_imx.h>
17 #include <spl.h>
18
19 #if defined(CONFIG_SPL_BUILD)
20
21 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)22 int spl_start_uboot(void)
23 {
24 /* Break into full U-Boot on 'c' */
25 if (serial_tstc() && serial_getc() == 'c')
26 return 1;
27
28 return 0;
29 }
30 #endif
31
32 static struct ddrc ddrc_regs_val = {
33 .mstr = 0x01040001,
34 .rfshtmg = 0x00400046,
35 .init1 = 0x00690000,
36 .init0 = 0x00020083,
37 .init3 = 0x09300004,
38 .init4 = 0x04080000,
39 .init5 = 0x00100004,
40 .rankctl = 0x0000033F,
41 .dramtmg0 = 0x09081109,
42 .dramtmg1 = 0x0007020d,
43 .dramtmg2 = 0x03040407,
44 .dramtmg3 = 0x00002006,
45 .dramtmg4 = 0x04020205,
46 .dramtmg5 = 0x03030202,
47 .dramtmg8 = 0x00000803,
48 .zqctl0 = 0x00800020,
49 .dfitmg0 = 0x02098204,
50 .dfitmg1 = 0x00030303,
51 .dfiupd0 = 0x80400003,
52 .dfiupd1 = 0x00100020,
53 .dfiupd2 = 0x80100004,
54 .addrmap4 = 0x00000F0F,
55 .odtcfg = 0x06000604,
56 .odtmap = 0x00000001,
57 .rfshtmg = 0x00400046,
58 .dramtmg0 = 0x09081109,
59 .addrmap0 = 0x0000001f,
60 .addrmap1 = 0x00080808,
61 .addrmap4 = 0x00000f0f,
62 .addrmap5 = 0x07070707,
63 .addrmap6 = 0x0f0f0707,
64 };
65
66 static struct ddrc_mp ddrc_mp_val = {
67 .pctrl_0 = 0x00000001,
68 };
69
70 static struct ddr_phy ddr_phy_regs_val = {
71 .phy_con0 = 0x17420f40,
72 .phy_con1 = 0x10210100,
73 .phy_con4 = 0x00060807,
74 .mdll_con0 = 0x1010007e,
75 .drvds_con0 = 0x00000d6e,
76 .cmd_sdll_con0 = 0x00000010,
77 .offset_lp_con0 = 0x0000000f,
78 .offset_rd_con0 = 0x08080808,
79 .offset_wr_con0 = 0x08080808,
80 };
81
82 static struct mx7_calibration calib_param = {
83 .num_val = 5,
84 .values = {
85 0x0E407304,
86 0x0E447304,
87 0x0E447306,
88 0x0E447304,
89 0x0E447304,
90 },
91 };
92
gpr_init(void)93 static void gpr_init(void)
94 {
95 struct iomuxc_gpr_base_regs *gpr_regs =
96 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
97 writel(0x4F400005, &gpr_regs->gpr[1]);
98 }
99
is_1g(void)100 static bool is_1g(void)
101 {
102 gpio_direction_input(IMX_GPIO_NR(1, 12));
103 return !gpio_get_value(IMX_GPIO_NR(1, 12));
104 }
105
ddr_init(void)106 static void ddr_init(void)
107 {
108 if (is_1g())
109 ddrc_regs_val.addrmap6 = 0x0f070707;
110
111 mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
112 &calib_param);
113 }
114
board_init_f(ulong dummy)115 void board_init_f(ulong dummy)
116 {
117 arch_cpu_init();
118 gpr_init();
119 board_early_init_f();
120 timer_init();
121 preloader_console_init();
122 ddr_init();
123 memset(__bss_start, 0, __bss_end - __bss_start);
124 board_init_r(NULL, 0);
125 }
126
reset_cpu(ulong addr)127 void reset_cpu(ulong addr)
128 {
129 }
130
131 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
132 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
133
134 static iomux_v3_cfg_t const usdhc3_pads[] = {
135 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 };
147
148 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
149 {USDHC3_BASE_ADDR},
150 };
151
board_mmc_getcd(struct mmc * mmc)152 int board_mmc_getcd(struct mmc *mmc)
153 {
154 /* Assume uSDHC3 emmc is always present */
155 return 1;
156 }
157
board_mmc_init(bd_t * bis)158 int board_mmc_init(bd_t *bis)
159 {
160 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
161 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
162 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
163 }
164 #endif
165