1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <console.h>
8 #include <i2c.h>
9 #include <init.h>
10 #include <pci.h>
11 #if !defined(CONFIG_SPL_BUILD)
12 #include <bootcount.h>
13 #endif
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <linux/mbus.h>
19 #ifdef CONFIG_NET
20 #include <netdev.h>
21 #endif
22 #include <u-boot/crc.h>
23 #include "theadorable.h"
24
25 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
26 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
31 #define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
32 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
33
34 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
35 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
36 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
37
38 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
39 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
40 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
41
42 #define GPIO_USB0_PWR_ON 18
43 #define GPIO_USB1_PWR_ON 19
44
45 #define PEX_SWITCH_NOT_FOUNT_LIMIT 3
46
47 #define STM_I2C_BUS 1
48 #define STM_I2C_ADDR 0x27
49 #define REBOOT_DELAY 1000 /* reboot-delay in ms */
50 #define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
51
52 /* DDR3 static configuration */
53 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
54 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
55 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
56 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
57 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
58 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
59 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
60 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
61 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
62 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
63
64 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
65 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
66 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
67 {0x000014A8, 0x00000101}, /* AXI Control Register */
68
69 /*
70 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
71 * training sequence
72 */
73 {0x000200e8, 0x3fff0e01},
74 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
75
76 {0x0001504, 0x7fffffe1}, /* CS0 Size */
77 {0x000150C, 0x00000000}, /* CS1 Size */
78 {0x0001514, 0x00000000}, /* CS2 Size */
79 {0x000151C, 0x00000000}, /* CS3 Size */
80
81 {0x00020220, 0x00000007}, /* Reserved */
82
83 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
84 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
85
86 {0x000015D0, 0x00000650}, /* MR0 */
87 {0x000015D4, 0x00000044}, /* MR1 */
88 {0x000015D8, 0x00000010}, /* MR2 */
89 {0x000015DC, 0x00000000}, /* MR3 */
90 {0x000015E0, 0x00000001},
91 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
92 {0x000015EC, 0xf800a225}, /* DDR PHY */
93
94 /* Recommended Settings from Marvell for 4 x 16 bit devices: */
95 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
96 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
97
98 {0x0, 0x0}
99 };
100
101 static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
102 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
103 };
104
105 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
106
107 /*
108 * Lane0 - PCIE0.0 X1 (to WIFI Module)
109 * Lane5 - SATA0
110 * Lane6 - SATA1
111 * Lane7 - SGMII0 (to Ethernet Phy)
112 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
113 * all other lanes are disabled
114 */
115 MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
116 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
117 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
118 PEX_BUS_DISABLED },
119 0x0060, serdes_change_m_phy
120 },
121 };
122
123 /*
124 * Define a board-specific detection pulse-width array for the SerDes PCIe
125 * interfaces. If not defined in the board code, the default of currently 2
126 * is used. Values from 0...3 are possible (2 bits).
127 */
128 u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
129
ddr3_get_static_ddr_mode(void)130 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
131 {
132 /* Only one mode supported for this board */
133 return &board_ddr_modes[0];
134 }
135
board_serdes_cfg_get(void)136 MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
137 {
138 return &theadorable_serdes_cfg[0];
139 }
140
board_sat_r_get(u8 dev_num,u8 reg)141 u8 board_sat_r_get(u8 dev_num, u8 reg)
142 {
143 /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
144 return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
145 }
146
board_early_init_f(void)147 int board_early_init_f(void)
148 {
149 /* Configure MPP */
150 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
151 writel(0x03300000, MVEBU_MPP_BASE + 0x04);
152 writel(0x00000033, MVEBU_MPP_BASE + 0x08);
153 writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
154 writel(0x11110000, MVEBU_MPP_BASE + 0x10);
155 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
156 writel(0x00000000, MVEBU_MPP_BASE + 0x18);
157 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
158 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
159
160 /* Configure GPIO */
161 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
162 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
163 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
164 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
165 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
166 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
167
168 return 0;
169 }
170
board_init(void)171 int board_init(void)
172 {
173 int ret;
174
175 /* adress of boot parameters */
176 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
177
178 /*
179 * Map SPI devices via MBUS so that they can be accessed via
180 * the SPI direct access mode
181 */
182 mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
183 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
184 mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
185 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
186
187 /*
188 * Set RX Channel Control 0 Register:
189 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
190 * to 3 (1/1) results in a more stable USB connection.
191 */
192 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
193 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
194 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
195
196 /* Toggle USB power */
197 ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
198 if (ret < 0)
199 return ret;
200 gpio_direction_output(GPIO_USB0_PWR_ON, 0);
201 ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
202 if (ret < 0)
203 return ret;
204 gpio_direction_output(GPIO_USB1_PWR_ON, 0);
205 mdelay(1);
206 gpio_set_value(GPIO_USB0_PWR_ON, 1);
207 gpio_set_value(GPIO_USB1_PWR_ON, 1);
208
209 return 0;
210 }
211
checkboard(void)212 int checkboard(void)
213 {
214 board_fpga_add();
215
216 return 0;
217 }
218
219 #ifdef CONFIG_NET
board_eth_init(bd_t * bis)220 int board_eth_init(bd_t *bis)
221 {
222 cpu_eth_init(bis); /* Built in controller(s) come first */
223 return pci_eth_init(bis);
224 }
225 #endif
226
227 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
board_late_init(void)228 int board_late_init(void)
229 {
230 pci_dev_t bdf;
231 ulong bootcount;
232
233 /*
234 * Check if the PEX switch is detected (somtimes its not available
235 * on the PCIe bus). In this case, try to recover by issuing a
236 * soft-reset or even a power-cycle, depending on the bootcounter
237 * value.
238 */
239 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
240 if (bdf == -1) {
241 unsigned long start_time = get_timer(0);
242 u8 i2c_buf[8];
243 int ret;
244
245 /* PEX switch not found! */
246 bootcount = bootcount_load();
247 printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
248 bootcount);
249
250 /*
251 * The user can exit this boot-loop in the error case by
252 * hitting Ctrl-C. So wait some time for this key here.
253 */
254 printf("Continue booting with Ctrl-C, otherwise rebooting\n");
255 do {
256 /* Handle control-c and timeouts */
257 if (ctrlc()) {
258 printf("PEX error boot-loop aborted!\n");
259 return 0;
260 }
261 } while (get_timer(start_time) < ABORT_TIMEOUT);
262
263
264 /*
265 * At this stage the bootcounter has not been incremented
266 * yet. We need to do this manually here to get an actually
267 * working bootcounter in this error case.
268 */
269 bootcount_inc();
270
271 if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
272 printf("Issuing power-switch via uC!\n");
273
274 printf("Issuing power-switch via uC!\n");
275 i2c_set_bus_num(STM_I2C_BUS);
276 i2c_buf[0] = STM_I2C_ADDR << 1;
277 i2c_buf[1] = 0xc5; /* cmd */
278 i2c_buf[2] = 0x01; /* enable */
279 /* Delay before reboot */
280 i2c_buf[3] = REBOOT_DELAY & 0x00ff;
281 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
282 /* Delay before shutdown */
283 i2c_buf[5] = 0x00;
284 i2c_buf[6] = 0x00;
285 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
286
287 ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
288 if (ret) {
289 printf("I2C write error (ret=%d)\n", ret);
290 printf("Issuing soft-reset...\n");
291 /* default handling: SOFT reset */
292 do_reset(NULL, 0, 0, NULL);
293 }
294
295 /* Wait for power-cycle to occur... */
296 printf("Waiting for power-cycle via uC...\n");
297 while (1)
298 ;
299 } else {
300 printf("Issuing soft-reset...\n");
301 /* default handling: SOFT reset */
302 do_reset(NULL, 0, 0, NULL);
303 }
304 }
305
306 return 0;
307 }
308 #endif
309
310 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
do_pcie_test(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])311 int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
312 {
313 pci_dev_t bdf;
314 u16 ven_id, dev_id;
315
316 if (argc != 3)
317 return cmd_usage(cmdtp);
318
319 ven_id = simple_strtoul(argv[1], NULL, 16);
320 dev_id = simple_strtoul(argv[2], NULL, 16);
321
322 printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
323 ven_id, dev_id);
324
325 /*
326 * Check if the PCIe device is detected (somtimes its not available
327 * on the PCIe bus)
328 */
329 bdf = pci_find_device(ven_id, dev_id, 0);
330 if (bdf == -1) {
331 /* PCIe device not found! */
332 printf("Failed to find PCIe device\n");
333 } else {
334 /* PCIe device found! */
335 printf("PCIe device found, resetting board...\n");
336
337 /* default handling: SOFT reset */
338 do_reset(NULL, 0, 0, NULL);
339 }
340
341 return 0;
342 }
343
344 U_BOOT_CMD(
345 pcie, 3, 0, do_pcie_test,
346 "Test for presence of a PCIe device",
347 "<VendorID> <DeviceID>"
348 );
349 #endif
350