1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for TI AM43XX based boards
6 *
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <eeprom.h>
12 #include <env.h>
13 #include <i2c.h>
14 #include <init.h>
15 #include <linux/errno.h>
16 #include <spl.h>
17 #include <usb.h>
18 #include <asm/omap_sec_common.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mux.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/emif.h>
25 #include <asm/omap_common.h>
26 #include "../common/board_detect.h"
27 #include "board.h"
28 #include <power/pmic.h>
29 #include <power/tps65218.h>
30 #include <power/tps62362.h>
31 #include <miiphy.h>
32 #include <cpsw.h>
33 #include <linux/usb/gadget.h>
34 #include <dwc3-uboot.h>
35 #include <dwc3-omap-uboot.h>
36 #include <ti-usb-phy-uboot.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
41
42 /*
43 * Read header information from EEPROM into global structure.
44 */
45 #ifdef CONFIG_TI_I2C_BOARD_DETECT
do_board_detect(void)46 void do_board_detect(void)
47 {
48 /* Ensure I2C is initialized for EEPROM access*/
49 gpi2c_init();
50 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
51 CONFIG_EEPROM_CHIP_ADDRESS))
52 printf("ti_i2c_eeprom_init failed\n");
53 }
54 #endif
55
56 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
57
58 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
59 { /* 19.2 MHz */
60 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
61 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
62 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
63 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
64 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
65 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
66 },
67 { /* 24 MHz */
68 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
69 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
70 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
71 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
72 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
73 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
74 },
75 { /* 25 MHz */
76 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
77 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
78 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
79 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
80 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
81 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
82 },
83 { /* 26 MHz */
84 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
86 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
87 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
88 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
89 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
90 },
91 };
92
93 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
94 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
95 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
96 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
97 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
98 };
99
100 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
101 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
102 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
103 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
104 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
105 };
106
107 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
108 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
109 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
110 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
111 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
112 };
113
114 const struct dpll_params gp_evm_dpll_ddr = {
115 50, 2, 1, -1, 2, -1, -1};
116
117 static const struct dpll_params idk_dpll_ddr = {
118 400, 23, 1, -1, 2, -1, -1
119 };
120
121 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
122 0x00500050,
123 0x00350035,
124 0x00350035,
125 0x00350035,
126 0x00350035,
127 0x00350035,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x40001000,
141 0x08102040
142 };
143
144 const struct ctrl_ioregs ioregs_lpddr2 = {
145 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
146 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
147 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
148 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
149 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
150 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
151 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
152 .emif_sdram_config_ext = 0x1,
153 };
154
155 const struct emif_regs emif_regs_lpddr2 = {
156 .sdram_config = 0x808012BA,
157 .ref_ctrl = 0x0000040D,
158 .sdram_tim1 = 0xEA86B411,
159 .sdram_tim2 = 0x103A094A,
160 .sdram_tim3 = 0x0F6BA37F,
161 .read_idle_ctrl = 0x00050000,
162 .zq_config = 0x50074BE4,
163 .temp_alert_config = 0x0,
164 .emif_rd_wr_lvl_rmp_win = 0x0,
165 .emif_rd_wr_lvl_rmp_ctl = 0x0,
166 .emif_rd_wr_lvl_ctl = 0x0,
167 .emif_ddr_phy_ctlr_1 = 0x0E284006,
168 .emif_rd_wr_exec_thresh = 0x80000405,
169 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
170 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
171 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
172 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
173 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
174 .emif_prio_class_serv_map = 0x80000001,
175 .emif_connect_id_serv_1_map = 0x80000094,
176 .emif_connect_id_serv_2_map = 0x00000000,
177 .emif_cos_config = 0x000FFFFF
178 };
179
180 const struct ctrl_ioregs ioregs_ddr3 = {
181 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
182 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
183 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
184 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
185 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
186 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
187 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
188 .emif_sdram_config_ext = 0xc163,
189 };
190
191 const struct emif_regs ddr3_emif_regs_400Mhz = {
192 .sdram_config = 0x638413B2,
193 .ref_ctrl = 0x00000C30,
194 .sdram_tim1 = 0xEAAAD4DB,
195 .sdram_tim2 = 0x266B7FDA,
196 .sdram_tim3 = 0x107F8678,
197 .read_idle_ctrl = 0x00050000,
198 .zq_config = 0x50074BE4,
199 .temp_alert_config = 0x0,
200 .emif_ddr_phy_ctlr_1 = 0x0E004008,
201 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
202 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
203 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
204 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
205 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
206 .emif_rd_wr_lvl_rmp_win = 0x0,
207 .emif_rd_wr_lvl_rmp_ctl = 0x0,
208 .emif_rd_wr_lvl_ctl = 0x0,
209 .emif_rd_wr_exec_thresh = 0x80000405,
210 .emif_prio_class_serv_map = 0x80000001,
211 .emif_connect_id_serv_1_map = 0x80000094,
212 .emif_connect_id_serv_2_map = 0x00000000,
213 .emif_cos_config = 0x000FFFFF
214 };
215
216 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
217 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
218 .sdram_config = 0x638413B2,
219 .ref_ctrl = 0x00000C30,
220 .sdram_tim1 = 0xEAAAD4DB,
221 .sdram_tim2 = 0x266B7FDA,
222 .sdram_tim3 = 0x107F8678,
223 .read_idle_ctrl = 0x00050000,
224 .zq_config = 0x50074BE4,
225 .temp_alert_config = 0x0,
226 .emif_ddr_phy_ctlr_1 = 0x0E004008,
227 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
228 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
229 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
230 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
231 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
232 .emif_rd_wr_exec_thresh = 0x80000405,
233 .emif_prio_class_serv_map = 0x80000001,
234 .emif_connect_id_serv_1_map = 0x80000094,
235 .emif_connect_id_serv_2_map = 0x00000000,
236 .emif_cos_config = 0x000FFFFF
237 };
238
239 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
240 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
241 .sdram_config = 0x638413B2,
242 .ref_ctrl = 0x00000C30,
243 .sdram_tim1 = 0xEAAAD4DB,
244 .sdram_tim2 = 0x266B7FDA,
245 .sdram_tim3 = 0x107F8678,
246 .read_idle_ctrl = 0x00050000,
247 .zq_config = 0x50074BE4,
248 .temp_alert_config = 0x0,
249 .emif_ddr_phy_ctlr_1 = 0x00048008,
250 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
251 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
252 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
253 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
254 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
255 .emif_rd_wr_exec_thresh = 0x80000405,
256 .emif_prio_class_serv_map = 0x80000001,
257 .emif_connect_id_serv_1_map = 0x80000094,
258 .emif_connect_id_serv_2_map = 0x00000000,
259 .emif_cos_config = 0x000FFFFF
260 };
261
262 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
263 .sdram_config = 0x638413b2,
264 .sdram_config2 = 0x00000000,
265 .ref_ctrl = 0x00000c30,
266 .sdram_tim1 = 0xeaaad4db,
267 .sdram_tim2 = 0x266b7fda,
268 .sdram_tim3 = 0x107f8678,
269 .read_idle_ctrl = 0x00050000,
270 .zq_config = 0x50074be4,
271 .temp_alert_config = 0x0,
272 .emif_ddr_phy_ctlr_1 = 0x0e084008,
273 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
274 .emif_ddr_ext_phy_ctrl_2 = 0x89,
275 .emif_ddr_ext_phy_ctrl_3 = 0x90,
276 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
277 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
278 .emif_rd_wr_lvl_rmp_win = 0x0,
279 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
280 .emif_rd_wr_lvl_ctl = 0x00000000,
281 .emif_rd_wr_exec_thresh = 0x80000000,
282 .emif_prio_class_serv_map = 0x80000001,
283 .emif_connect_id_serv_1_map = 0x80000094,
284 .emif_connect_id_serv_2_map = 0x00000000,
285 .emif_cos_config = 0x000FFFFF
286 };
287
288 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
289 .sdram_config = 0x61a11b32,
290 .sdram_config2 = 0x00000000,
291 .ref_ctrl = 0x00000c30,
292 .sdram_tim1 = 0xeaaad4db,
293 .sdram_tim2 = 0x266b7fda,
294 .sdram_tim3 = 0x107f8678,
295 .read_idle_ctrl = 0x00050000,
296 .zq_config = 0x50074be4,
297 .temp_alert_config = 0x00000000,
298 .emif_ddr_phy_ctlr_1 = 0x00008009,
299 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
300 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
301 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
302 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
303 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
304 .emif_rd_wr_lvl_rmp_win = 0x00000000,
305 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
306 .emif_rd_wr_lvl_ctl = 0x00000000,
307 .emif_rd_wr_exec_thresh = 0x00000405,
308 .emif_prio_class_serv_map = 0x00000000,
309 .emif_connect_id_serv_1_map = 0x00000000,
310 .emif_connect_id_serv_2_map = 0x00000000,
311 .emif_cos_config = 0x00ffffff
312 };
313
emif_get_ext_phy_ctrl_const_regs(const u32 ** regs,u32 * size)314 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
315 {
316 if (board_is_eposevm()) {
317 *regs = ext_phy_ctrl_const_base_lpddr2;
318 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
319 }
320
321 return;
322 }
323
get_dpll_ddr_params(void)324 const struct dpll_params *get_dpll_ddr_params(void)
325 {
326 int ind = get_sys_clk_index();
327
328 if (board_is_eposevm())
329 return &epos_evm_dpll_ddr[ind];
330 else if (board_is_evm() || board_is_sk())
331 return &gp_evm_dpll_ddr;
332 else if (board_is_idk())
333 return &idk_dpll_ddr;
334
335 printf(" Board '%s' not supported\n", board_ti_get_name());
336 return NULL;
337 }
338
339
340 /*
341 * get_opp_offset:
342 * Returns the index for safest OPP of the device to boot.
343 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
344 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
345 * This data is read from dev_attribute register which is e-fused.
346 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
347 * OPP available. Lowest OPP starts with min_off. So returning the
348 * bit with rightmost '0'.
349 */
get_opp_offset(int max_off,int min_off)350 static int get_opp_offset(int max_off, int min_off)
351 {
352 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
353 int opp, offset, i;
354
355 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
356 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
357
358 for (i = max_off; i >= min_off; i--) {
359 offset = opp & (1 << i);
360 if (!offset)
361 return i;
362 }
363
364 return min_off;
365 }
366
get_dpll_mpu_params(void)367 const struct dpll_params *get_dpll_mpu_params(void)
368 {
369 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
370 u32 ind = get_sys_clk_index();
371
372 return &dpll_mpu[ind][opp];
373 }
374
get_dpll_core_params(void)375 const struct dpll_params *get_dpll_core_params(void)
376 {
377 int ind = get_sys_clk_index();
378
379 return &dpll_core[ind];
380 }
381
get_dpll_per_params(void)382 const struct dpll_params *get_dpll_per_params(void)
383 {
384 int ind = get_sys_clk_index();
385
386 return &dpll_per[ind];
387 }
388
scale_vcores_generic(u32 m)389 void scale_vcores_generic(u32 m)
390 {
391 int mpu_vdd, ddr_volt;
392
393 #ifndef CONFIG_DM_I2C
394 if (i2c_probe(TPS65218_CHIP_PM))
395 return;
396 #else
397 if (power_tps65218_init(0))
398 return;
399 #endif
400
401 switch (m) {
402 case 1000:
403 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
404 break;
405 case 800:
406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
407 break;
408 case 720:
409 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
410 break;
411 case 600:
412 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
413 break;
414 case 300:
415 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
416 break;
417 default:
418 puts("Unknown MPU clock, not scaling\n");
419 return;
420 }
421
422 /* Set DCDC1 (CORE) voltage to 1.1V */
423 if (tps65218_voltage_update(TPS65218_DCDC1,
424 TPS65218_DCDC_VOLT_SEL_1100MV)) {
425 printf("%s failure\n", __func__);
426 return;
427 }
428
429 /* Set DCDC2 (MPU) voltage */
430 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
431 printf("%s failure\n", __func__);
432 return;
433 }
434
435 if (board_is_eposevm())
436 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
437 else
438 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
439
440 /* Set DCDC3 (DDR) voltage */
441 if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
442 printf("%s failure\n", __func__);
443 return;
444 }
445 }
446
scale_vcores_idk(u32 m)447 void scale_vcores_idk(u32 m)
448 {
449 int mpu_vdd;
450
451 #ifndef CONFIG_DM_I2C
452 if (i2c_probe(TPS62362_I2C_ADDR))
453 return;
454 #else
455 if (power_tps62362_init(0))
456 return;
457 #endif
458
459 switch (m) {
460 case 1000:
461 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
462 break;
463 case 800:
464 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
465 break;
466 case 720:
467 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
468 break;
469 case 600:
470 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
471 break;
472 case 300:
473 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
474 break;
475 default:
476 puts("Unknown MPU clock, not scaling\n");
477 return;
478 }
479 /* Set VDD_MPU voltage */
480 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
481 printf("%s failure\n", __func__);
482 return;
483 }
484 }
gpi2c_init(void)485 void gpi2c_init(void)
486 {
487 /* When needed to be invoked prior to BSS initialization */
488 static bool first_time = true;
489
490 if (first_time) {
491 enable_i2c0_pin_mux();
492 #ifndef CONFIG_DM_I2C
493 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
494 CONFIG_SYS_OMAP24_I2C_SLAVE);
495 #endif
496 first_time = false;
497 }
498 }
499
scale_vcores(void)500 void scale_vcores(void)
501 {
502 const struct dpll_params *mpu_params;
503
504 /* Ensure I2C is initialized for PMIC configuration */
505 gpi2c_init();
506
507 /* Get the frequency */
508 mpu_params = get_dpll_mpu_params();
509
510 if (board_is_idk())
511 scale_vcores_idk(mpu_params->m);
512 else
513 scale_vcores_generic(mpu_params->m);
514 }
515
set_uart_mux_conf(void)516 void set_uart_mux_conf(void)
517 {
518 enable_uart0_pin_mux();
519 }
520
set_mux_conf_regs(void)521 void set_mux_conf_regs(void)
522 {
523 enable_board_pin_mux();
524 }
525
enable_vtt_regulator(void)526 static void enable_vtt_regulator(void)
527 {
528 u32 temp;
529
530 /* enable module */
531 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
532
533 /* enable output for GPIO5_7 */
534 writel(GPIO_SETDATAOUT(7),
535 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
536 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
537 temp = temp & ~(GPIO_OE_ENABLE(7));
538 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
539 }
540
541 enum {
542 RTC_BOARD_EPOS = 1,
543 RTC_BOARD_EVM14,
544 RTC_BOARD_EVM12,
545 RTC_BOARD_GPEVM,
546 RTC_BOARD_SK,
547 };
548
549 /*
550 * In the rtc_only+DRR in self-refresh boot path we have the board type info
551 * in the rtc scratch pad register hence we bypass the costly i2c reads to
552 * eeprom and directly programthe board name string
553 */
rtc_only_update_board_type(u32 btype)554 void rtc_only_update_board_type(u32 btype)
555 {
556 const char *name = "";
557 const char *rev = "1.0";
558
559 switch (btype) {
560 case RTC_BOARD_EPOS:
561 name = "AM43EPOS";
562 break;
563 case RTC_BOARD_EVM14:
564 name = "AM43__GP";
565 rev = "1.4";
566 break;
567 case RTC_BOARD_EVM12:
568 name = "AM43__GP";
569 rev = "1.2";
570 break;
571 case RTC_BOARD_GPEVM:
572 name = "AM43__GP";
573 break;
574 case RTC_BOARD_SK:
575 name = "AM43__SK";
576 break;
577 }
578 ti_i2c_eeprom_am_set(name, rev);
579 }
580
rtc_only_get_board_type(void)581 u32 rtc_only_get_board_type(void)
582 {
583 if (board_is_eposevm())
584 return RTC_BOARD_EPOS;
585 else if (board_is_evm_14_or_later())
586 return RTC_BOARD_EVM14;
587 else if (board_is_evm_12_or_later())
588 return RTC_BOARD_EVM12;
589 else if (board_is_gpevm())
590 return RTC_BOARD_GPEVM;
591 else if (board_is_sk())
592 return RTC_BOARD_SK;
593
594 return 0;
595 }
596
sdram_init(void)597 void sdram_init(void)
598 {
599 /*
600 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
601 * GP EMV has 1GB DDR3 connected to EMIF
602 * along with VTT regulator.
603 */
604 if (board_is_eposevm()) {
605 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
606 } else if (board_is_evm_14_or_later()) {
607 enable_vtt_regulator();
608 config_ddr(0, &ioregs_ddr3, NULL, NULL,
609 &ddr3_emif_regs_400Mhz_production, 0);
610 } else if (board_is_evm_12_or_later()) {
611 enable_vtt_regulator();
612 config_ddr(0, &ioregs_ddr3, NULL, NULL,
613 &ddr3_emif_regs_400Mhz_beta, 0);
614 } else if (board_is_evm()) {
615 enable_vtt_regulator();
616 config_ddr(0, &ioregs_ddr3, NULL, NULL,
617 &ddr3_emif_regs_400Mhz, 0);
618 } else if (board_is_sk()) {
619 config_ddr(400, &ioregs_ddr3, NULL, NULL,
620 &ddr3_sk_emif_regs_400Mhz, 0);
621 } else if (board_is_idk()) {
622 config_ddr(400, &ioregs_ddr3, NULL, NULL,
623 &ddr3_idk_emif_regs_400Mhz, 0);
624 }
625 }
626 #endif
627
628 /* setup board specific PMIC */
power_init_board(void)629 int power_init_board(void)
630 {
631 int rc;
632 #ifndef CONFIG_DM_I2C
633 struct pmic *p = NULL;
634 #endif
635 if (board_is_idk()) {
636 rc = power_tps62362_init(0);
637 if (rc)
638 goto done;
639 #ifndef CONFIG_DM_I2C
640 p = pmic_get("TPS62362");
641 if (!p || pmic_probe(p))
642 goto done;
643 #endif
644 puts("PMIC: TPS62362\n");
645 } else {
646 rc = power_tps65218_init(0);
647 if (rc)
648 goto done;
649 #ifndef CONFIG_DM_I2C
650 p = pmic_get("TPS65218_PMIC");
651 if (!p || pmic_probe(p))
652 goto done;
653 #endif
654 puts("PMIC: TPS65218\n");
655 }
656 done:
657 return 0;
658 }
659
board_init(void)660 int board_init(void)
661 {
662 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
663 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
664 modena_init0_bw_integer, modena_init0_watermark_0;
665
666 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
667 gpmc_init();
668
669 /*
670 * Call this to initialize *ctrl again
671 */
672 hw_data_init();
673
674 /* Clear all important bits for DSS errata that may need to be tweaked*/
675 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
676 MREQPRIO_0_SAB_INIT0_MASK;
677
678 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
679
680 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
681 BW_LIMITER_BW_FRAC_MASK;
682
683 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
684 BW_LIMITER_BW_INT_MASK;
685
686 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
687 BW_LIMITER_BW_WATERMARK_MASK;
688
689 /* Setting MReq Priority of the DSS*/
690 mreqprio_0 |= 0x77;
691
692 /*
693 * Set L3 Fast Configuration Register
694 * Limiting bandwith for ARM core to 700 MBPS
695 */
696 modena_init0_bw_fractional |= 0x10;
697 modena_init0_bw_integer |= 0x3;
698
699 writel(mreqprio_0, &cdev->mreqprio_0);
700 writel(mreqprio_1, &cdev->mreqprio_1);
701
702 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
703 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
704 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
705
706 return 0;
707 }
708
709 #ifdef CONFIG_BOARD_LATE_INIT
710 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
device_okay(const char * path)711 static int device_okay(const char *path)
712 {
713 int node;
714
715 node = fdt_path_offset(gd->fdt_blob, path);
716 if (node < 0)
717 return 0;
718
719 return fdtdec_get_is_enabled(gd->fdt_blob, node);
720 }
721 #endif
722
board_late_init(void)723 int board_late_init(void)
724 {
725 struct udevice *dev;
726 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
727 set_board_info_env(NULL);
728
729 /*
730 * Default FIT boot on HS devices. Non FIT images are not allowed
731 * on HS devices.
732 */
733 if (get_device_type() == HS_DEVICE)
734 env_set("boot_fit", "1");
735 #endif
736
737 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
738 if (device_okay("/ocp/omap_dwc3@48380000"))
739 enable_usb_clocks(0);
740 if (device_okay("/ocp/omap_dwc3@483c0000"))
741 enable_usb_clocks(1);
742 #endif
743
744 /* Just probe the potentially supported cdce913 device */
745 uclass_get_device(UCLASS_CLK, 0, &dev);
746
747 return 0;
748 }
749 #endif
750
751 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
752 #ifdef CONFIG_USB_DWC3
753 static struct dwc3_device usb_otg_ss1 = {
754 .maximum_speed = USB_SPEED_HIGH,
755 .base = USB_OTG_SS1_BASE,
756 .tx_fifo_resize = false,
757 .index = 0,
758 };
759
760 static struct dwc3_omap_device usb_otg_ss1_glue = {
761 .base = (void *)USB_OTG_SS1_GLUE_BASE,
762 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
763 .index = 0,
764 };
765
766 static struct ti_usb_phy_device usb_phy1_device = {
767 .usb2_phy_power = (void *)USB2_PHY1_POWER,
768 .index = 0,
769 };
770
771 static struct dwc3_device usb_otg_ss2 = {
772 .maximum_speed = USB_SPEED_HIGH,
773 .base = USB_OTG_SS2_BASE,
774 .tx_fifo_resize = false,
775 .index = 1,
776 };
777
778 static struct dwc3_omap_device usb_otg_ss2_glue = {
779 .base = (void *)USB_OTG_SS2_GLUE_BASE,
780 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
781 .index = 1,
782 };
783
784 static struct ti_usb_phy_device usb_phy2_device = {
785 .usb2_phy_power = (void *)USB2_PHY2_POWER,
786 .index = 1,
787 };
788
usb_gadget_handle_interrupts(int index)789 int usb_gadget_handle_interrupts(int index)
790 {
791 u32 status;
792
793 status = dwc3_omap_uboot_interrupt_status(index);
794 if (status)
795 dwc3_uboot_handle_interrupt(index);
796
797 return 0;
798 }
799 #endif /* CONFIG_USB_DWC3 */
800
801 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
board_usb_init(int index,enum usb_init_type init)802 int board_usb_init(int index, enum usb_init_type init)
803 {
804 enable_usb_clocks(index);
805 #ifdef CONFIG_USB_DWC3
806 switch (index) {
807 case 0:
808 if (init == USB_INIT_DEVICE) {
809 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
810 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
811 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
812 ti_usb_phy_uboot_init(&usb_phy1_device);
813 dwc3_uboot_init(&usb_otg_ss1);
814 }
815 break;
816 case 1:
817 if (init == USB_INIT_DEVICE) {
818 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
819 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
820 ti_usb_phy_uboot_init(&usb_phy2_device);
821 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
822 dwc3_uboot_init(&usb_otg_ss2);
823 }
824 break;
825 default:
826 printf("Invalid Controller Index\n");
827 }
828 #endif
829
830 return 0;
831 }
832
board_usb_cleanup(int index,enum usb_init_type init)833 int board_usb_cleanup(int index, enum usb_init_type init)
834 {
835 #ifdef CONFIG_USB_DWC3
836 switch (index) {
837 case 0:
838 case 1:
839 if (init == USB_INIT_DEVICE) {
840 ti_usb_phy_uboot_exit(index);
841 dwc3_uboot_exit(index);
842 dwc3_omap_uboot_exit(index);
843 }
844 break;
845 default:
846 printf("Invalid Controller Index\n");
847 }
848 #endif
849 disable_usb_clocks(index);
850
851 return 0;
852 }
853 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
854 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
855
856 #ifdef CONFIG_DRIVER_TI_CPSW
857
cpsw_control(int enabled)858 static void cpsw_control(int enabled)
859 {
860 /* Additional controls can be added here */
861 return;
862 }
863
864 static struct cpsw_slave_data cpsw_slaves[] = {
865 {
866 .slave_reg_ofs = 0x208,
867 .sliver_reg_ofs = 0xd80,
868 .phy_addr = 16,
869 },
870 {
871 .slave_reg_ofs = 0x308,
872 .sliver_reg_ofs = 0xdc0,
873 .phy_addr = 1,
874 },
875 };
876
877 static struct cpsw_platform_data cpsw_data = {
878 .mdio_base = CPSW_MDIO_BASE,
879 .cpsw_base = CPSW_BASE,
880 .mdio_div = 0xff,
881 .channels = 8,
882 .cpdma_reg_ofs = 0x800,
883 .slaves = 1,
884 .slave_data = cpsw_slaves,
885 .ale_reg_ofs = 0xd00,
886 .ale_entries = 1024,
887 .host_port_reg_ofs = 0x108,
888 .hw_stats_reg_ofs = 0x900,
889 .bd_ram_ofs = 0x2000,
890 .mac_control = (1 << 5),
891 .control = cpsw_control,
892 .host_port_num = 0,
893 .version = CPSW_CTRL_VERSION_2,
894 };
895
board_eth_init(bd_t * bis)896 int board_eth_init(bd_t *bis)
897 {
898 int rv;
899 uint8_t mac_addr[6];
900 uint32_t mac_hi, mac_lo;
901
902 /* try reading mac address from efuse */
903 mac_lo = readl(&cdev->macid0l);
904 mac_hi = readl(&cdev->macid0h);
905 mac_addr[0] = mac_hi & 0xFF;
906 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
907 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
908 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
909 mac_addr[4] = mac_lo & 0xFF;
910 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
911
912 if (!env_get("ethaddr")) {
913 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
914 if (is_valid_ethaddr(mac_addr))
915 eth_env_set_enetaddr("ethaddr", mac_addr);
916 }
917
918 mac_lo = readl(&cdev->macid1l);
919 mac_hi = readl(&cdev->macid1h);
920 mac_addr[0] = mac_hi & 0xFF;
921 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
922 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
923 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
924 mac_addr[4] = mac_lo & 0xFF;
925 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
926
927 if (!env_get("eth1addr")) {
928 if (is_valid_ethaddr(mac_addr))
929 eth_env_set_enetaddr("eth1addr", mac_addr);
930 }
931
932 if (board_is_eposevm()) {
933 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
934 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
935 cpsw_slaves[0].phy_addr = 16;
936 } else if (board_is_sk()) {
937 writel(RGMII_MODE_ENABLE, &cdev->miisel);
938 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
939 cpsw_slaves[0].phy_addr = 4;
940 cpsw_slaves[1].phy_addr = 5;
941 } else if (board_is_idk()) {
942 writel(RGMII_MODE_ENABLE, &cdev->miisel);
943 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
944 cpsw_slaves[0].phy_addr = 0;
945 } else {
946 writel(RGMII_MODE_ENABLE, &cdev->miisel);
947 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
948 cpsw_slaves[0].phy_addr = 0;
949 }
950
951 rv = cpsw_register(&cpsw_data);
952 if (rv < 0)
953 printf("Error %d registering CPSW switch\n", rv);
954
955 return rv;
956 }
957 #endif
958
959 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)960 int ft_board_setup(void *blob, bd_t *bd)
961 {
962 ft_cpu_setup(blob, bd);
963
964 return 0;
965 }
966 #endif
967
968 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
board_fit_config_name_match(const char * name)969 int board_fit_config_name_match(const char *name)
970 {
971 bool eeprom_read = board_ti_was_eeprom_read();
972
973 if (!strcmp(name, "am4372-generic") && !eeprom_read)
974 return 0;
975 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
976 return 0;
977 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
978 return 0;
979 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
980 return 0;
981 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
982 return 0;
983 else
984 return -1;
985 }
986 #endif
987
988 #ifdef CONFIG_DTB_RESELECT
embedded_dtb_select(void)989 int embedded_dtb_select(void)
990 {
991 do_board_detect();
992 fdtdec_setup();
993
994 return 0;
995 }
996 #endif
997
998 #ifdef CONFIG_TI_SECURE_DEVICE
board_fit_image_post_process(void ** p_image,size_t * p_size)999 void board_fit_image_post_process(void **p_image, size_t *p_size)
1000 {
1001 secure_boot_verify_image(p_image, p_size);
1002 }
1003
board_tee_image_process(ulong tee_image,size_t tee_size)1004 void board_tee_image_process(ulong tee_image, size_t tee_size)
1005 {
1006 secure_tee_install((u32)tee_image);
1007 }
1008
1009 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1010 #endif
1011