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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2004-2011
4  * Texas Instruments, <www.ti.com>
5  *
6  * Author :
7  *	Manikandan Pillai <mani.pillai@ti.com>
8  *
9  * Derived from Beagle Board and 3430 SDP code by
10  *	Richard Woodruff <r-woodruff2@ti.com>
11  *	Syed Mohammed Khasim <khasim@ti.com>
12  */
13 #include <common.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <ns16550.h>
17 #include <netdev.h>
18 #include <serial.h>
19 #include <asm/io.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mux.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/gpio.h>
25 #include <i2c.h>
26 #include <twl4030.h>
27 #include <asm/mach-types.h>
28 #include <asm/omap_musb.h>
29 #include <linux/mtd/rawnand.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/musb.h>
33 #include "evm.h"
34 
35 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
36 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 static u32 omap3_evm_version;
41 
get_omap3_evm_rev(void)42 u32 get_omap3_evm_rev(void)
43 {
44 	return omap3_evm_version;
45 }
46 
omap3_evm_get_revision(void)47 static void omap3_evm_get_revision(void)
48 {
49 #if defined(CONFIG_CMD_NET)
50 	/*
51 	 * Board revision can be ascertained only by identifying
52 	 * the Ethernet chipset.
53 	 */
54 	unsigned int smsc_id;
55 
56 	/* Ethernet PHY ID is stored at ID_REV register */
57 	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
58 	printf("Read back SMSC id 0x%x\n", smsc_id);
59 
60 	switch (smsc_id) {
61 	/* SMSC9115 chipset */
62 	case 0x01150000:
63 		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
64 		break;
65 	/* SMSC 9220 chipset */
66 	case 0x92200000:
67 	default:
68 		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
69        }
70 #else /* !CONFIG_CMD_NET */
71 #if defined(CONFIG_STATIC_BOARD_REV)
72 	/* Look for static defintion of the board revision */
73 	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
74 #else
75 	/* Fallback to the default above */
76 	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
77 #endif /* CONFIG_STATIC_BOARD_REV */
78 #endif /* CONFIG_CMD_NET */
79 }
80 
81 #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
82 /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
omap3_evm_need_extvbus(void)83 u8 omap3_evm_need_extvbus(void)
84 {
85 	u8 retval = 0;
86 
87 	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
88 		retval = 1;
89 
90 	return retval;
91 }
92 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
93 
94 /*
95  * Routine: board_init
96  * Description: Early hardware init.
97  */
board_init(void)98 int board_init(void)
99 {
100 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
101 	/* board id for Linux */
102 	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
103 	/* boot param addr */
104 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
105 
106 	return 0;
107 }
108 
109 #if defined(CONFIG_SPL_OS_BOOT)
spl_start_uboot(void)110 int spl_start_uboot(void)
111 {
112 	/* break into full u-boot on 'c' */
113 	if (serial_tstc() && serial_getc() == 'c')
114 		return 1;
115 
116 	return 0;
117 }
118 #endif /* CONFIG_SPL_OS_BOOT */
119 
120 #if defined(CONFIG_SPL_BUILD)
121 /*
122  * Routine: get_board_mem_timings
123  * Description: If we use SPL then there is no x-loader nor config header
124  * so we have to setup the DDR timings ourself on the first bank.  This
125  * provides the timing values back to the function that configures
126  * the memory.
127  */
get_board_mem_timings(struct board_sdrc_timings * timings)128 void get_board_mem_timings(struct board_sdrc_timings *timings)
129 {
130 	int pop_mfr, pop_id;
131 
132 	/*
133 	 * We need to identify what PoP memory is on the board so that
134 	 * we know what timings to use.  To map the ID values please see
135 	 * nand_ids.c
136 	 */
137 	identify_nand_chip(&pop_mfr, &pop_id);
138 
139 	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
140 		/* 256MB DDR */
141 		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
142 		timings->ctrla = HYNIX_V_ACTIMA_200;
143 		timings->ctrlb = HYNIX_V_ACTIMB_200;
144 	} else {
145 		/* 128MB DDR */
146 		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
147 		timings->ctrla = MICRON_V_ACTIMA_165;
148 		timings->ctrlb = MICRON_V_ACTIMB_165;
149 	}
150 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
151 	timings->mr = MICRON_V_MR_165;
152 }
153 #endif /* CONFIG_SPL_BUILD */
154 
155 #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
156 static struct musb_hdrc_config musb_config = {
157 	.multipoint     = 1,
158 	.dyn_fifo       = 1,
159 	.num_eps        = 16,
160 	.ram_bits       = 12,
161 };
162 
163 static struct omap_musb_board_data musb_board_data = {
164 	.interface_type	= MUSB_INTERFACE_ULPI,
165 };
166 
167 static struct musb_hdrc_platform_data musb_plat = {
168 #if defined(CONFIG_USB_MUSB_HOST)
169 	.mode           = MUSB_HOST,
170 #elif defined(CONFIG_USB_MUSB_GADGET)
171 	.mode		= MUSB_PERIPHERAL,
172 #else
173 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
174 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
175 	.config         = &musb_config,
176 	.power          = 100,
177 	.platform_ops	= &omap2430_ops,
178 	.board_data	= &musb_board_data,
179 };
180 #endif /* CONFIG_USB_MUSB_OMAP2PLUS */
181 
182 /*
183  * Routine: misc_init_r
184  * Description: Init ethernet (done here so udelay works)
185  */
misc_init_r(void)186 int misc_init_r(void)
187 {
188 	twl4030_power_init();
189 
190 #ifdef CONFIG_SYS_I2C_OMAP24XX
191 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
192 #endif
193 
194 #if defined(CONFIG_CMD_NET)
195 	setup_net_chip();
196 #endif
197 	omap3_evm_get_revision();
198 
199 #if defined(CONFIG_CMD_NET)
200 	reset_net_chip();
201 #endif
202 	omap_die_id_display();
203 
204 #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
205 	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
206 #endif
207 
208 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
209 	omap_die_id_usbethaddr();
210 #endif
211 	return 0;
212 }
213 
214 /*
215  * Routine: set_muxconf_regs
216  * Description: Setting up the configuration Mux registers specific to the
217  *		hardware. Many pins need to be moved from protect to primary
218  *		mode.
219  */
set_muxconf_regs(void)220 void set_muxconf_regs(void)
221 {
222 	MUX_EVM();
223 }
224 
225 #if defined(CONFIG_CMD_NET)
226 /*
227  * Routine: setup_net_chip
228  * Description: Setting up the configuration GPMC registers specific to the
229  *		Ethernet hardware.
230  */
setup_net_chip(void)231 static void setup_net_chip(void)
232 {
233 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
234 
235 	/* Configure GPMC registers */
236 	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
237 	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
238 	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
239 	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
240 	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
241 	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
242 	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
243 
244 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
245 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
246 	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
247 	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
248 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
249 	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
250 		&ctrl_base->gpmc_nadv_ale);
251 }
252 
253 /**
254  * Reset the ethernet chip.
255  */
reset_net_chip(void)256 static void reset_net_chip(void)
257 {
258 	int ret;
259 	int rst_gpio;
260 
261 	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
262 		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
263 	} else {
264 		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
265 	}
266 
267 	ret = gpio_request(rst_gpio, "");
268 	if (ret < 0) {
269 		printf("Unable to get GPIO %d\n", rst_gpio);
270 		return ;
271 	}
272 
273 	/* Configure as output */
274 	gpio_direction_output(rst_gpio, 0);
275 
276 	/* Send a pulse on the GPIO pin */
277 	gpio_set_value(rst_gpio, 1);
278 	udelay(1);
279 	gpio_set_value(rst_gpio, 0);
280 	udelay(1);
281 	gpio_set_value(rst_gpio, 1);
282 }
283 
board_eth_init(bd_t * bis)284 int board_eth_init(bd_t *bis)
285 {
286 #if defined(CONFIG_SMC911X)
287 	env_set("ethaddr", NULL);
288 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
289 #else
290 	return 0;
291 #endif
292 }
293 #endif /* CONFIG_CMD_NET */
294 
295 #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)296 int board_mmc_init(bd_t *bis)
297 {
298 	return omap_mmc_init(0, 0, 0, -1, -1);
299 }
300 
board_mmc_power_init(void)301 void board_mmc_power_init(void)
302 {
303 	twl4030_power_mmc_init(0);
304 }
305 #endif /* CONFIG_MMC */
306 
307 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
board_eth_init(bd_t * bis)308 int board_eth_init(bd_t *bis)
309 {
310 	return usb_eth_initialize(bis);
311 }
312 #endif /* CONFIG_USB_ETHER */
313