1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5 * Copyright (C) 2014-2019, Toradex AG
6 * copied from nitrogen6x
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <env.h>
12 #include <init.h>
13
14 #include <asm/arch/clock.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/mx6-ddr.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/bootm.h>
22 #include <asm/gpio.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/sata.h>
26 #include <asm/mach-imx/video.h>
27 #include <cpu.h>
28 #include <dm/platform_data/serial_mxc.h>
29 #include <fsl_esdhc_imx.h>
30 #include <imx_thermal.h>
31 #include <miiphy.h>
32 #include <netdev.h>
33 #include <cpu.h>
34
35 #include "../common/tdx-cfg-block.h"
36 #ifdef CONFIG_TDX_CMD_IMX_MFGR
37 #include "pf0100.h"
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
56
57 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
59 PAD_CTL_SRE_SLOW)
60
61 #define NO_PULLUP ( \
62 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
63 PAD_CTL_SRE_SLOW)
64
65 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
67 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
68
69 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
70
dram_init(void)71 int dram_init(void)
72 {
73 /* use the DDR controllers configured size */
74 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
75 (ulong)imx_ddr_size());
76
77 return 0;
78 }
79
80 /* Colibri UARTA */
81 iomux_v3_cfg_t const uart1_pads[] = {
82 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84 };
85
86 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
87 /* Colibri MMC */
88 iomux_v3_cfg_t const usdhc1_pads[] = {
89 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
96 # define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
97 };
98
99 /* eMMC */
100 iomux_v3_cfg_t const usdhc3_pads[] = {
101 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
102 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
103 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
104 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
105 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
106 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
107 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
108 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
109 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
110 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
111 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 };
113 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
114
115 iomux_v3_cfg_t const enet_pads[] = {
116 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 };
127
setup_iomux_enet(void)128 static void setup_iomux_enet(void)
129 {
130 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
131 }
132
133 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
134 iomux_v3_cfg_t const gpio_pads[] = {
135 /* ADDRESS[17:18] [25] used as GPIO */
136 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
137 MUX_MODE_SION,
138 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
139 MUX_MODE_SION,
140 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
141 MUX_MODE_SION,
142 /* ADDRESS[19:24] used as GPIO */
143 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
144 MUX_MODE_SION,
145 MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
146 MUX_MODE_SION,
147 MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
148 MUX_MODE_SION,
149 MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
150 MUX_MODE_SION,
151 MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
152 MUX_MODE_SION,
153 MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
154 MUX_MODE_SION,
155 /* DATA[16:29] [31] used as GPIO */
156 MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
157 MUX_MODE_SION,
158 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
159 MUX_MODE_SION,
160 MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
161 MUX_MODE_SION,
162 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
163 MUX_MODE_SION,
164 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
165 MUX_MODE_SION,
166 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
167 MUX_MODE_SION,
168 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
169 MUX_MODE_SION,
170 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
171 MUX_MODE_SION,
172 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
173 MUX_MODE_SION,
174 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
175 MUX_MODE_SION,
176 MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
177 MUX_MODE_SION,
178 MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
179 MUX_MODE_SION,
180 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
181 MUX_MODE_SION,
182 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
183 MUX_MODE_SION,
184 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
185 MUX_MODE_SION,
186 /* DQM[0:3] used as GPIO */
187 MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
188 MUX_MODE_SION,
189 MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
190 MUX_MODE_SION,
191 MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
192 MUX_MODE_SION,
193 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
194 MUX_MODE_SION,
195 /* RDY used as GPIO */
196 MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
197 MUX_MODE_SION,
198 /* ADDRESS[16] DATA[30] used as GPIO */
199 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
200 MUX_MODE_SION,
201 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
202 MUX_MODE_SION,
203 /* CSI pins used as GPIO */
204 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
205 MUX_MODE_SION,
206 MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
207 MUX_MODE_SION,
208 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
209 MUX_MODE_SION,
210 MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
211 MUX_MODE_SION,
212 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
213 MUX_MODE_SION,
214 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
215 MUX_MODE_SION,
216 MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
217 MUX_MODE_SION,
218 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
219 MUX_MODE_SION,
220 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
221 MUX_MODE_SION,
222 MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
223 MUX_MODE_SION,
224 MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
225 MUX_MODE_SION,
226 MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
227 MUX_MODE_SION,
228 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
229 MUX_MODE_SION,
230 /* GPIO */
231 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
232 MUX_MODE_SION,
233 MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
234 MUX_MODE_SION,
235 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
236 MUX_MODE_SION,
237 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
238 MUX_MODE_SION,
239 MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
240 MUX_MODE_SION,
241 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
242 MUX_MODE_SION,
243 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
244 MUX_MODE_SION,
245 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
246 MUX_MODE_SION,
247 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
248 MUX_MODE_SION,
249 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
250 MUX_MODE_SION,
251 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
252 MUX_MODE_SION,
253 /* USBH_OC */
254 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
255 /* USBC_ID */
256 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
257 /* USBC_DET */
258 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
259 };
260
setup_iomux_gpio(void)261 static void setup_iomux_gpio(void)
262 {
263 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
264 }
265
266 iomux_v3_cfg_t const usb_pads[] = {
267 /* USBH_PEN */
268 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
269 # define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
270 };
271
272 /*
273 * UARTs are used in DTE mode, switch the mode on all UARTs before
274 * any pinmuxing connects a (DCE) output to a transceiver output.
275 */
276 #define UCR3 0x88 /* FIFO Control Register */
277 #define UCR3_RI BIT(8) /* RIDELT DTE mode */
278 #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
279 #define UFCR 0x90 /* FIFO Control Register */
280 #define UFCR_DCEDTE BIT(6) /* DCE=0 */
281
setup_dtemode_uart(void)282 static void setup_dtemode_uart(void)
283 {
284 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
285 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
286 setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
287
288 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
289 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
290 clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
291 }
292
setup_iomux_uart(void)293 static void setup_iomux_uart(void)
294 {
295 setup_dtemode_uart();
296 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
297 }
298
299 #ifdef CONFIG_USB_EHCI_MX6
board_ehci_hcd_init(int port)300 int board_ehci_hcd_init(int port)
301 {
302 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
303 return 0;
304 }
305 #endif
306
307 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
308 /* use the following sequence: eMMC, MMC */
309 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
310 {USDHC3_BASE_ADDR},
311 {USDHC1_BASE_ADDR},
312 };
313
board_mmc_getcd(struct mmc * mmc)314 int board_mmc_getcd(struct mmc *mmc)
315 {
316 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
317 int ret = true; /* default: assume inserted */
318
319 switch (cfg->esdhc_base) {
320 case USDHC1_BASE_ADDR:
321 gpio_request(GPIO_MMC_CD, "MMC_CD");
322 gpio_direction_input(GPIO_MMC_CD);
323 ret = !gpio_get_value(GPIO_MMC_CD);
324 break;
325 }
326
327 return ret;
328 }
329
board_mmc_init(bd_t * bis)330 int board_mmc_init(bd_t *bis)
331 {
332 struct src *psrc = (struct src *)SRC_BASE_ADDR;
333 unsigned reg = readl(&psrc->sbmr1) >> 11;
334 /*
335 * Upon reading BOOT_CFG register the following map is done:
336 * Bit 11 and 12 of BOOT_CFG register can determine the current
337 * mmc port
338 * 0x1 SD1
339 * 0x2 SD2
340 * 0x3 SD4
341 */
342
343 switch (reg & 0x3) {
344 case 0x0:
345 imx_iomux_v3_setup_multiple_pads(
346 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
347 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
348 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
349 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
350 break;
351 case 0x2:
352 imx_iomux_v3_setup_multiple_pads(
353 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
354 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
355 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
356 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
357 break;
358 default:
359 puts("MMC boot device not available");
360 }
361
362 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
363 }
364 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
365
board_phy_config(struct phy_device * phydev)366 int board_phy_config(struct phy_device *phydev)
367 {
368 if (phydev->drv->config)
369 phydev->drv->config(phydev);
370
371 return 0;
372 }
373
board_eth_init(bd_t * bis)374 int board_eth_init(bd_t *bis)
375 {
376 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
377 uint32_t base = IMX_FEC_BASE;
378 struct mii_dev *bus = NULL;
379 struct phy_device *phydev = NULL;
380 int ret;
381
382 /* provide the PHY clock from the i.MX 6 */
383 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
384 if (ret)
385 return ret;
386
387 /* set gpr1[ENET_CLK_SEL] */
388 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
389
390 setup_iomux_enet();
391
392 #ifdef CONFIG_FEC_MXC
393 bus = fec_get_miibus(base, -1);
394 if (!bus)
395 return 0;
396
397 /* scan PHY 1..7 */
398 phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
399 if (!phydev) {
400 free(bus);
401 puts("no PHY found\n");
402 return 0;
403 }
404
405 phy_reset(phydev);
406 printf("using PHY at %d\n", phydev->addr);
407 ret = fec_probe(bis, -1, base, bus, phydev);
408 if (ret) {
409 printf("FEC MXC: %s:failed\n", __func__);
410 free(phydev);
411 free(bus);
412 }
413 #endif /* CONFIG_FEC_MXC */
414
415 return 0;
416 }
417
418 static iomux_v3_cfg_t const pwr_intb_pads[] = {
419 /*
420 * the bootrom sets the iomux to vselect, potentially connecting
421 * two outputs. Set this back to GPIO
422 */
423 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
424 };
425
426 #if defined(CONFIG_VIDEO_IPUV3)
427
428 static iomux_v3_cfg_t const backlight_pads[] = {
429 /* Backlight On */
430 MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
431 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
432 /* Backlight PWM, used as GPIO in U-Boot */
433 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
434 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
435 MUX_MODE_SION,
436 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
437 };
438
439 static iomux_v3_cfg_t const rgb_pads[] = {
440 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
441 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
442 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
443 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
444 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
445 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
462 };
463
do_enable_hdmi(struct display_info_t const * dev)464 static void do_enable_hdmi(struct display_info_t const *dev)
465 {
466 imx_enable_hdmi_phy();
467 }
468
enable_rgb(struct display_info_t const * dev)469 static void enable_rgb(struct display_info_t const *dev)
470 {
471 imx_iomux_v3_setup_multiple_pads(
472 rgb_pads,
473 ARRAY_SIZE(rgb_pads));
474 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
475 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
476 }
477
detect_default(struct display_info_t const * dev)478 static int detect_default(struct display_info_t const *dev)
479 {
480 (void) dev;
481 return 1;
482 }
483
484 struct display_info_t const displays[] = {{
485 .bus = -1,
486 .addr = 0,
487 .pixfmt = IPU_PIX_FMT_RGB24,
488 .detect = detect_hdmi,
489 .enable = do_enable_hdmi,
490 .mode = {
491 .name = "HDMI",
492 .refresh = 60,
493 .xres = 1024,
494 .yres = 768,
495 .pixclock = 15385,
496 .left_margin = 220,
497 .right_margin = 40,
498 .upper_margin = 21,
499 .lower_margin = 7,
500 .hsync_len = 60,
501 .vsync_len = 10,
502 .sync = FB_SYNC_EXT,
503 .vmode = FB_VMODE_NONINTERLACED
504 } }, {
505 .bus = -1,
506 .addr = 0,
507 .pixfmt = IPU_PIX_FMT_RGB666,
508 .detect = detect_default,
509 .enable = enable_rgb,
510 .mode = {
511 .name = "vga-rgb",
512 .refresh = 60,
513 .xres = 640,
514 .yres = 480,
515 .pixclock = 33000,
516 .left_margin = 48,
517 .right_margin = 16,
518 .upper_margin = 31,
519 .lower_margin = 11,
520 .hsync_len = 96,
521 .vsync_len = 2,
522 .sync = 0,
523 .vmode = FB_VMODE_NONINTERLACED
524 } }, {
525 .bus = -1,
526 .addr = 0,
527 .pixfmt = IPU_PIX_FMT_RGB666,
528 .enable = enable_rgb,
529 .mode = {
530 .name = "wvga-rgb",
531 .refresh = 60,
532 .xres = 800,
533 .yres = 480,
534 .pixclock = 25000,
535 .left_margin = 40,
536 .right_margin = 88,
537 .upper_margin = 33,
538 .lower_margin = 10,
539 .hsync_len = 128,
540 .vsync_len = 2,
541 .sync = 0,
542 .vmode = FB_VMODE_NONINTERLACED
543 } } };
544 size_t display_count = ARRAY_SIZE(displays);
545
setup_display(void)546 static void setup_display(void)
547 {
548 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
549 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
550 int reg;
551
552 enable_ipu_clock();
553 imx_setup_hdmi();
554 /* Turn on LDB0,IPU,IPU DI0 clocks */
555 reg = __raw_readl(&mxc_ccm->CCGR3);
556 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
557 writel(reg, &mxc_ccm->CCGR3);
558
559 /* set LDB0, LDB1 clk select to 011/011 */
560 reg = readl(&mxc_ccm->cs2cdr);
561 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
562 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
563 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
564 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
565 writel(reg, &mxc_ccm->cs2cdr);
566
567 reg = readl(&mxc_ccm->cscmr2);
568 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
569 writel(reg, &mxc_ccm->cscmr2);
570
571 reg = readl(&mxc_ccm->chsccdr);
572 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
573 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
574 writel(reg, &mxc_ccm->chsccdr);
575
576 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
577 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
578 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
579 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
580 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
581 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
582 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
583 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
584 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
585 writel(reg, &iomux->gpr[2]);
586
587 reg = readl(&iomux->gpr[3]);
588 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
589 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
590 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
591 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
592 writel(reg, &iomux->gpr[3]);
593
594 /* backlight unconditionally on for now */
595 imx_iomux_v3_setup_multiple_pads(backlight_pads,
596 ARRAY_SIZE(backlight_pads));
597 /* use 0 for EDT 7", use 1 for LG fullHD panel */
598 gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
599 gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
600 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
601 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
602 }
603
604 /*
605 * Backlight off before OS handover
606 */
board_preboot_os(void)607 void board_preboot_os(void)
608 {
609 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
610 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
611 }
612 #endif /* defined(CONFIG_VIDEO_IPUV3) */
613
board_early_init_f(void)614 int board_early_init_f(void)
615 {
616 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
617 ARRAY_SIZE(pwr_intb_pads));
618 setup_iomux_uart();
619
620 return 0;
621 }
622
623 /*
624 * Do not overwrite the console
625 * Use always serial for U-Boot console
626 */
overwrite_console(void)627 int overwrite_console(void)
628 {
629 return 1;
630 }
631
board_init(void)632 int board_init(void)
633 {
634 /* address of boot parameters */
635 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
636
637 #if defined(CONFIG_VIDEO_IPUV3)
638 setup_display();
639 #endif
640
641 #ifdef CONFIG_TDX_CMD_IMX_MFGR
642 (void) pmic_init();
643 #endif
644
645 #ifdef CONFIG_SATA
646 setup_sata();
647 #endif
648
649 setup_iomux_gpio();
650
651 return 0;
652 }
653
654 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)655 int board_late_init(void)
656 {
657 #if defined(CONFIG_REVISION_TAG) && \
658 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
659 char env_str[256];
660 u32 rev;
661
662 rev = get_board_rev();
663 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
664 env_set("board_rev", env_str);
665 #endif
666
667 #ifdef CONFIG_CMD_USB_SDP
668 if (is_boot_from_usb()) {
669 printf("Serial Downloader recovery mode, using sdp command\n");
670 env_set("bootdelay", "0");
671 env_set("bootcmd", "sdp 0");
672 }
673 #endif /* CONFIG_CMD_USB_SDP */
674
675 return 0;
676 }
677 #endif /* CONFIG_BOARD_LATE_INIT */
678
checkboard(void)679 int checkboard(void)
680 {
681 char it[] = " IT";
682 int minc, maxc;
683
684 switch (get_cpu_temp_grade(&minc, &maxc)) {
685 case TEMP_AUTOMOTIVE:
686 case TEMP_INDUSTRIAL:
687 break;
688 case TEMP_EXTCOMMERCIAL:
689 default:
690 it[0] = 0;
691 };
692 printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
693 is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
694 (gd->ram_size == 0x20000000) ? "512" : "256", it);
695 return 0;
696 }
697
698 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)699 int ft_board_setup(void *blob, bd_t *bd)
700 {
701 u32 cma_size;
702
703 ft_common_board_setup(blob, bd);
704
705 cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
706 cma_size = min((u32)(gd->ram_size >> 1), cma_size);
707
708 fdt_setprop_u32(blob,
709 fdt_path_offset(blob, "/reserved-memory/linux,cma"),
710 "size",
711 cma_size);
712 return 0;
713 }
714 #endif
715
716 #ifdef CONFIG_CMD_BMODE
717 static const struct boot_mode board_boot_modes[] = {
718 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
719 {NULL, 0},
720 };
721 #endif
722
misc_init_r(void)723 int misc_init_r(void)
724 {
725 #ifdef CONFIG_CMD_BMODE
726 add_board_boot_modes(board_boot_modes);
727 #endif
728 return 0;
729 }
730
731 #ifdef CONFIG_LDO_BYPASS_CHECK
732 /* TODO, use external pmic, for now always ldo_enable */
ldo_mode_set(int ldo_bypass)733 void ldo_mode_set(int ldo_bypass)
734 {
735 return;
736 }
737 #endif
738
739 #ifdef CONFIG_SPL_BUILD
740 #include <spl.h>
741 #include <linux/libfdt.h>
742 #include "asm/arch/mx6dl-ddr.h"
743 #include "asm/arch/iomux.h"
744 #include "asm/arch/crm_regs.h"
745
746 static int mx6s_dcd_table[] = {
747 /* ddr-setup.cfg */
748
749 MX6_IOM_DRAM_SDQS0, 0x00000030,
750 MX6_IOM_DRAM_SDQS1, 0x00000030,
751 MX6_IOM_DRAM_SDQS2, 0x00000030,
752 MX6_IOM_DRAM_SDQS3, 0x00000030,
753 MX6_IOM_DRAM_SDQS4, 0x00000030,
754 MX6_IOM_DRAM_SDQS5, 0x00000030,
755 MX6_IOM_DRAM_SDQS6, 0x00000030,
756 MX6_IOM_DRAM_SDQS7, 0x00000030,
757
758 MX6_IOM_GRP_B0DS, 0x00000030,
759 MX6_IOM_GRP_B1DS, 0x00000030,
760 MX6_IOM_GRP_B2DS, 0x00000030,
761 MX6_IOM_GRP_B3DS, 0x00000030,
762 MX6_IOM_GRP_B4DS, 0x00000030,
763 MX6_IOM_GRP_B5DS, 0x00000030,
764 MX6_IOM_GRP_B6DS, 0x00000030,
765 MX6_IOM_GRP_B7DS, 0x00000030,
766 MX6_IOM_GRP_ADDDS, 0x00000030,
767 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
768 MX6_IOM_GRP_CTLDS, 0x00000030,
769
770 MX6_IOM_DRAM_DQM0, 0x00020030,
771 MX6_IOM_DRAM_DQM1, 0x00020030,
772 MX6_IOM_DRAM_DQM2, 0x00020030,
773 MX6_IOM_DRAM_DQM3, 0x00020030,
774 MX6_IOM_DRAM_DQM4, 0x00020030,
775 MX6_IOM_DRAM_DQM5, 0x00020030,
776 MX6_IOM_DRAM_DQM6, 0x00020030,
777 MX6_IOM_DRAM_DQM7, 0x00020030,
778
779 MX6_IOM_DRAM_CAS, 0x00020030,
780 MX6_IOM_DRAM_RAS, 0x00020030,
781 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
782 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
783
784 MX6_IOM_DRAM_RESET, 0x00020030,
785 MX6_IOM_DRAM_SDCKE0, 0x00003000,
786 MX6_IOM_DRAM_SDCKE1, 0x00003000,
787
788 MX6_IOM_DRAM_SDODT0, 0x00003030,
789 MX6_IOM_DRAM_SDODT1, 0x00003030,
790
791 /* (differential input) */
792 MX6_IOM_DDRMODE_CTL, 0x00020000,
793 /* (differential input) */
794 MX6_IOM_GRP_DDRMODE, 0x00020000,
795 /* disable ddr pullups */
796 MX6_IOM_GRP_DDRPKE, 0x00000000,
797 MX6_IOM_DRAM_SDBA2, 0x00000000,
798 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
799 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
800
801 /* Read data DQ Byte0-3 delay */
802 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
803 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
804 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
805 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
806 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
807 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
808 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
809 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
810
811 /*
812 * MDMISC mirroring interleaved (row/bank/col)
813 */
814 /* TODO: check what the RALAT field does */
815 MX6_MMDC_P0_MDMISC, 0x00081740,
816
817 /*
818 * MDSCR con_req
819 */
820 MX6_MMDC_P0_MDSCR, 0x00008000,
821
822
823 /* 800mhz_2x64mx16.cfg */
824
825 MX6_MMDC_P0_MDPDC, 0x0002002D,
826 MX6_MMDC_P0_MDCFG0, 0x2C305503,
827 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
828 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
829 MX6_MMDC_P0_MDRWD, 0x000026D2,
830 MX6_MMDC_P0_MDOR, 0x00301023,
831 MX6_MMDC_P0_MDOTC, 0x00333030,
832 MX6_MMDC_P0_MDPDC, 0x0002556D,
833 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
834 MX6_MMDC_P0_MDASP, 0x00000017,
835 /* DDR3 DATA BUS SIZE: 64BIT */
836 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
837 /* DDR3 DATA BUS SIZE: 32BIT */
838 MX6_MMDC_P0_MDCTL, 0x82190000,
839
840 /* Write commands to DDR */
841 /* Load Mode Registers */
842 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
843 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
844 MX6_MMDC_P0_MDSCR, 0x04008032,
845 MX6_MMDC_P0_MDSCR, 0x00008033,
846 MX6_MMDC_P0_MDSCR, 0x00048031,
847 MX6_MMDC_P0_MDSCR, 0x13208030,
848 /* ZQ calibration */
849 MX6_MMDC_P0_MDSCR, 0x04008040,
850
851 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
852 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
853 MX6_MMDC_P0_MDREF, 0x00005800,
854
855 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
856 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
857
858 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
859 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
860 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
861 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
862
863 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
864 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
865 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
866 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
867
868 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
869 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
870 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
871 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
872
873 MX6_MMDC_P0_MPMUR0, 0x00000800,
874 MX6_MMDC_P1_MPMUR0, 0x00000800,
875 MX6_MMDC_P0_MDSCR, 0x00000000,
876 MX6_MMDC_P0_MAPSR, 0x00011006,
877 };
878
879 static int mx6dl_dcd_table[] = {
880 /* ddr-setup.cfg */
881
882 MX6_IOM_DRAM_SDQS0, 0x00000030,
883 MX6_IOM_DRAM_SDQS1, 0x00000030,
884 MX6_IOM_DRAM_SDQS2, 0x00000030,
885 MX6_IOM_DRAM_SDQS3, 0x00000030,
886 MX6_IOM_DRAM_SDQS4, 0x00000030,
887 MX6_IOM_DRAM_SDQS5, 0x00000030,
888 MX6_IOM_DRAM_SDQS6, 0x00000030,
889 MX6_IOM_DRAM_SDQS7, 0x00000030,
890
891 MX6_IOM_GRP_B0DS, 0x00000030,
892 MX6_IOM_GRP_B1DS, 0x00000030,
893 MX6_IOM_GRP_B2DS, 0x00000030,
894 MX6_IOM_GRP_B3DS, 0x00000030,
895 MX6_IOM_GRP_B4DS, 0x00000030,
896 MX6_IOM_GRP_B5DS, 0x00000030,
897 MX6_IOM_GRP_B6DS, 0x00000030,
898 MX6_IOM_GRP_B7DS, 0x00000030,
899 MX6_IOM_GRP_ADDDS, 0x00000030,
900 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
901 MX6_IOM_GRP_CTLDS, 0x00000030,
902
903 MX6_IOM_DRAM_DQM0, 0x00020030,
904 MX6_IOM_DRAM_DQM1, 0x00020030,
905 MX6_IOM_DRAM_DQM2, 0x00020030,
906 MX6_IOM_DRAM_DQM3, 0x00020030,
907 MX6_IOM_DRAM_DQM4, 0x00020030,
908 MX6_IOM_DRAM_DQM5, 0x00020030,
909 MX6_IOM_DRAM_DQM6, 0x00020030,
910 MX6_IOM_DRAM_DQM7, 0x00020030,
911
912 MX6_IOM_DRAM_CAS, 0x00020030,
913 MX6_IOM_DRAM_RAS, 0x00020030,
914 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
915 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
916
917 MX6_IOM_DRAM_RESET, 0x00020030,
918 MX6_IOM_DRAM_SDCKE0, 0x00003000,
919 MX6_IOM_DRAM_SDCKE1, 0x00003000,
920
921 MX6_IOM_DRAM_SDODT0, 0x00003030,
922 MX6_IOM_DRAM_SDODT1, 0x00003030,
923
924 /* (differential input) */
925 MX6_IOM_DDRMODE_CTL, 0x00020000,
926 /* (differential input) */
927 MX6_IOM_GRP_DDRMODE, 0x00020000,
928 /* disable ddr pullups */
929 MX6_IOM_GRP_DDRPKE, 0x00000000,
930 MX6_IOM_DRAM_SDBA2, 0x00000000,
931 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
932 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
933
934 /* Read data DQ Byte0-3 delay */
935 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
936 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
937 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
938 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
939 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
940 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
941 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
942 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
943
944 /*
945 * MDMISC mirroring interleaved (row/bank/col)
946 */
947 /* TODO: check what the RALAT field does */
948 MX6_MMDC_P0_MDMISC, 0x00081740,
949
950 /*
951 * MDSCR con_req
952 */
953 MX6_MMDC_P0_MDSCR, 0x00008000,
954
955
956 /* 800mhz_2x64mx16.cfg */
957
958 MX6_MMDC_P0_MDPDC, 0x0002002D,
959 MX6_MMDC_P0_MDCFG0, 0x2C305503,
960 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
961 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
962 MX6_MMDC_P0_MDRWD, 0x000026D2,
963 MX6_MMDC_P0_MDOR, 0x00301023,
964 MX6_MMDC_P0_MDOTC, 0x00333030,
965 MX6_MMDC_P0_MDPDC, 0x0002556D,
966 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
967 MX6_MMDC_P0_MDASP, 0x00000017,
968 /* DDR3 DATA BUS SIZE: 64BIT */
969 MX6_MMDC_P0_MDCTL, 0x821A0000,
970 /* DDR3 DATA BUS SIZE: 32BIT */
971 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
972
973 /* Write commands to DDR */
974 /* Load Mode Registers */
975 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
976 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
977 MX6_MMDC_P0_MDSCR, 0x04008032,
978 MX6_MMDC_P0_MDSCR, 0x00008033,
979 MX6_MMDC_P0_MDSCR, 0x00048031,
980 MX6_MMDC_P0_MDSCR, 0x13208030,
981 /* ZQ calibration */
982 MX6_MMDC_P0_MDSCR, 0x04008040,
983
984 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
985 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
986 MX6_MMDC_P0_MDREF, 0x00005800,
987
988 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
989 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
990
991 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
992 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
993 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
994 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
995
996 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
997 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
998 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
999 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1000
1001 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1002 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1003 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1004 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1005
1006 MX6_MMDC_P0_MPMUR0, 0x00000800,
1007 MX6_MMDC_P1_MPMUR0, 0x00000800,
1008 MX6_MMDC_P0_MDSCR, 0x00000000,
1009 MX6_MMDC_P0_MAPSR, 0x00011006,
1010 };
1011
ccgr_init(void)1012 static void ccgr_init(void)
1013 {
1014 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1015
1016 writel(0x00C03F3F, &ccm->CCGR0);
1017 writel(0x0030FC03, &ccm->CCGR1);
1018 writel(0x0FFFFFF3, &ccm->CCGR2);
1019 writel(0x3FF0300F, &ccm->CCGR3);
1020 writel(0x00FFF300, &ccm->CCGR4);
1021 writel(0x0F0000F3, &ccm->CCGR5);
1022 writel(0x000003FF, &ccm->CCGR6);
1023
1024 /*
1025 * Setup CCM_CCOSR register as follows:
1026 *
1027 * cko1_en = 1 --> CKO1 enabled
1028 * cko1_div = 111 --> divide by 8
1029 * cko1_sel = 1011 --> ahb_clk_root
1030 *
1031 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1032 */
1033 writel(0x000000FB, &ccm->ccosr);
1034 }
1035
ddr_init(int * table,int size)1036 static void ddr_init(int *table, int size)
1037 {
1038 int i;
1039
1040 for (i = 0; i < size / 2 ; i++)
1041 writel(table[2 * i + 1], table[2 * i]);
1042 }
1043
spl_dram_init(void)1044 static void spl_dram_init(void)
1045 {
1046 int minc, maxc;
1047
1048 switch (get_cpu_temp_grade(&minc, &maxc)) {
1049 case TEMP_COMMERCIAL:
1050 case TEMP_EXTCOMMERCIAL:
1051 if (is_cpu_type(MXC_CPU_MX6DL)) {
1052 puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1053 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1054 } else {
1055 puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1056 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1057 }
1058 break;
1059 case TEMP_INDUSTRIAL:
1060 case TEMP_AUTOMOTIVE:
1061 default:
1062 if (is_cpu_type(MXC_CPU_MX6DL)) {
1063 puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1064 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1065 } else {
1066 puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1067 ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1068 }
1069 break;
1070 };
1071 udelay(100);
1072 }
1073
1074 static iomux_v3_cfg_t const gpio_reset_pad[] = {
1075 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1076 MUX_MODE_SION
1077 #define GPIO_NRESET IMX_GPIO_NR(6, 27)
1078 };
1079
1080 #define IMX_RESET_CAUSE_POR 0x00011
nreset_out(void)1081 static void nreset_out(void)
1082 {
1083 int reset_cause = get_imx_reset_cause();
1084
1085 if (reset_cause != IMX_RESET_CAUSE_POR) {
1086 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1087 ARRAY_SIZE(gpio_reset_pad));
1088 gpio_direction_output(GPIO_NRESET, 1);
1089 udelay(100);
1090 gpio_direction_output(GPIO_NRESET, 0);
1091 }
1092 }
1093
board_init_f(ulong dummy)1094 void board_init_f(ulong dummy)
1095 {
1096 /* setup AIPS and disable watchdog */
1097 arch_cpu_init();
1098
1099 ccgr_init();
1100 gpr_init();
1101
1102 /* iomux */
1103 board_early_init_f();
1104
1105 /* setup GP timer */
1106 timer_init();
1107
1108 /* UART clocks enabled and gd valid - init serial console */
1109 preloader_console_init();
1110
1111 /* Make sure we use dte mode */
1112 setup_dtemode_uart();
1113
1114 /* DDR initialization */
1115 spl_dram_init();
1116
1117 /* Clear the BSS. */
1118 memset(__bss_start, 0, __bss_end - __bss_start);
1119
1120 /* Assert nReset_Out */
1121 nreset_out();
1122
1123 /* load/boot image from boot device */
1124 board_init_r(NULL, 0);
1125 }
1126
reset_cpu(ulong addr)1127 void reset_cpu(ulong addr)
1128 {
1129 }
1130
1131 #endif /* CONFIG_SPL_BUILD */
1132
1133 static struct mxc_serial_platdata mxc_serial_plat = {
1134 .reg = (struct mxc_uart *)UART1_BASE,
1135 .use_dte = true,
1136 };
1137
1138 U_BOOT_DEVICE(mxc_serial) = {
1139 .name = "serial_mxc",
1140 .platdata = &mxc_serial_plat,
1141 };
1142