• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7  * Author: Markus Niebel <markus.niebel@tq-group.com>
8  */
9 
10 #include <init.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/sys_proto.h>
16 #include <env.h>
17 #include <linux/errno.h>
18 #include <asm/gpio.h>
19 #include <asm/io.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/spi.h>
22 #include <common.h>
23 #include <fsl_esdhc_imx.h>
24 #include <linux/libfdt.h>
25 #include <i2c.h>
26 #include <mmc.h>
27 #include <power/pfuze100_pmic.h>
28 #include <power/pmic.h>
29 #include <spi_flash.h>
30 
31 #include "tqma6_bb.h"
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
36 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37 
38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
39 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
40 
41 #define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
42 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
43 
44 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
45 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
46 
47 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 
50 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
51 	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
52 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
53 
dram_init(void)54 int dram_init(void)
55 {
56 	gd->ram_size = imx_ddr_size();
57 
58 	return 0;
59 }
60 
61 static const uint16_t tqma6_emmc_dsr = 0x0100;
62 
63 /* eMMC on USDHCI3 always present */
64 static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
65 	NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK,		USDHC_PAD_CTRL),
66 	NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD,		USDHC_PAD_CTRL),
67 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0,	USDHC_PAD_CTRL),
68 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1,	USDHC_PAD_CTRL),
69 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2,	USDHC_PAD_CTRL),
70 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3,	USDHC_PAD_CTRL),
71 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4,	USDHC_PAD_CTRL),
72 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5,	USDHC_PAD_CTRL),
73 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6,	USDHC_PAD_CTRL),
74 	NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7,	USDHC_PAD_CTRL),
75 	/* eMMC reset */
76 	NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET,	GPIO_OUT_PAD_CTRL),
77 };
78 
79 /*
80  * According to board_mmc_init() the following map is done:
81  * (U-Boot device node)    (Physical Port)
82  * mmc0                    eMMC (SD3) on TQMa6
83  * mmc1 .. n               optional slots used on baseboard
84  */
85 struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
86 	.esdhc_base = USDHC3_BASE_ADDR,
87 	.max_bus_width = 8,
88 };
89 
board_mmc_getcd(struct mmc * mmc)90 int board_mmc_getcd(struct mmc *mmc)
91 {
92 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
93 	int ret = 0;
94 
95 	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
96 		/* eMMC/uSDHC3 is always present */
97 		ret = 1;
98 	else
99 		ret = tqma6_bb_board_mmc_getcd(mmc);
100 
101 	return ret;
102 }
103 
board_mmc_getwp(struct mmc * mmc)104 int board_mmc_getwp(struct mmc *mmc)
105 {
106 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
107 	int ret = 0;
108 
109 	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
110 		/* eMMC/uSDHC3 is always present */
111 		ret = 0;
112 	else
113 		ret = tqma6_bb_board_mmc_getwp(mmc);
114 
115 	return ret;
116 }
117 
board_mmc_init(bd_t * bis)118 int board_mmc_init(bd_t *bis)
119 {
120 	imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
121 					 ARRAY_SIZE(tqma6_usdhc3_pads));
122 	tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
123 	if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
124 		puts("Warning: failed to initialize eMMC dev\n");
125 	} else {
126 		struct mmc *mmc = find_mmc_device(0);
127 		if (mmc)
128 			mmc_set_dsr(mmc, tqma6_emmc_dsr);
129 	}
130 
131 	tqma6_bb_board_mmc_init(bis);
132 
133 	return 0;
134 }
135 
136 static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
137 	/* SS1 */
138 	NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
139 	NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
140 	NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
141 	NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
142 };
143 
144 #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
145 
146 static unsigned const tqma6_ecspi1_cs[] = {
147 	TQMA6_SF_CS_GPIO,
148 };
149 
tqma6_iomuxc_spi(void)150 __weak void tqma6_iomuxc_spi(void)
151 {
152 	unsigned i;
153 
154 	for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
155 		gpio_direction_output(tqma6_ecspi1_cs[i], 1);
156 	imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
157 					 ARRAY_SIZE(tqma6_ecspi1_pads));
158 }
159 
160 #if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
board_spi_cs_gpio(unsigned bus,unsigned cs)161 int board_spi_cs_gpio(unsigned bus, unsigned cs)
162 {
163 	return ((bus == CONFIG_SF_DEFAULT_BUS) &&
164 		(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
165 }
166 #endif
167 
168 static struct i2c_pads_info tqma6_i2c3_pads = {
169 	/* I2C3: on board LM75, M24C64,  */
170 	.scl = {
171 		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
172 					 I2C_PAD_CTRL),
173 		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
174 					  I2C_PAD_CTRL),
175 		.gp = IMX_GPIO_NR(1, 5)
176 	},
177 	.sda = {
178 		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
179 					 I2C_PAD_CTRL),
180 		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
181 					  I2C_PAD_CTRL),
182 		.gp = IMX_GPIO_NR(1, 6)
183 	}
184 };
185 
tqma6_setup_i2c(void)186 static void tqma6_setup_i2c(void)
187 {
188 	int ret;
189 	/*
190 	 * use logical index for bus, e.g. I2C1 -> 0
191 	 * warn on error
192 	 */
193 	ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
194 	if (ret)
195 		printf("setup I2C3 failed: %d\n", ret);
196 }
197 
board_early_init_f(void)198 int board_early_init_f(void)
199 {
200 	return tqma6_bb_board_early_init_f();
201 }
202 
board_init(void)203 int board_init(void)
204 {
205 	/* address of boot parameters */
206 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
207 
208 	tqma6_iomuxc_spi();
209 	tqma6_setup_i2c();
210 
211 	tqma6_bb_board_init();
212 
213 	return 0;
214 }
215 
tqma6_get_boardname(void)216 static const char *tqma6_get_boardname(void)
217 {
218 	u32 cpurev = get_cpu_rev();
219 
220 	switch ((cpurev & 0xFF000) >> 12) {
221 	case MXC_CPU_MX6SOLO:
222 		return "TQMa6S";
223 		break;
224 	case MXC_CPU_MX6DL:
225 		return "TQMa6DL";
226 		break;
227 	case MXC_CPU_MX6D:
228 		return "TQMa6D";
229 		break;
230 	case MXC_CPU_MX6Q:
231 		return "TQMa6Q";
232 		break;
233 	default:
234 		return "??";
235 	};
236 }
237 
238 /* setup board specific PMIC */
power_init_board(void)239 int power_init_board(void)
240 {
241 	struct pmic *p;
242 	u32 reg, rev;
243 
244 	power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
245 	p = pmic_get("PFUZE100");
246 	if (p && !pmic_probe(p)) {
247 		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
248 		pmic_reg_read(p, PFUZE100_REVID, &rev);
249 		printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
250 	}
251 
252 	return 0;
253 }
254 
board_late_init(void)255 int board_late_init(void)
256 {
257 	env_set("board_name", tqma6_get_boardname());
258 
259 	tqma6_bb_board_late_init();
260 
261 	return 0;
262 }
263 
checkboard(void)264 int checkboard(void)
265 {
266 	printf("Board: %s on a %s\n", tqma6_get_boardname(),
267 	       tqma6_bb_get_boardname());
268 	return 0;
269 }
270 
271 /*
272  * Device Tree Support
273  */
274 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
275 #define MODELSTRLEN 32u
ft_board_setup(void * blob,bd_t * bd)276 int ft_board_setup(void *blob, bd_t *bd)
277 {
278 	char modelstr[MODELSTRLEN];
279 
280 	snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
281 		 tqma6_bb_get_boardname());
282 	do_fixup_by_path_string(blob, "/", "model", modelstr);
283 	fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
284 	/* bring in eMMC dsr settings */
285 	do_fixup_by_path_u32(blob,
286 			     "/soc/aips-bus@02100000/usdhc@02198000",
287 			     "dsr", tqma6_emmc_dsr, 2);
288 	tqma6_bb_ft_board_setup(blob, bd);
289 
290 	return 0;
291 }
292 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
293