1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 * Copyright (C) Jasbir Matharu
5 * Copyright (C) UDOO Team
6 *
7 * Author: Breno Lima <breno.lima@nxp.com>
8 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 */
10
11 #include <init.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <env.h>
20 #include <mmc.h>
21 #include <fsl_esdhc_imx.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/io.h>
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/sys_proto.h>
26 #include <spl.h>
27 #include <linux/sizes.h>
28 #include <common.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <netdev.h>
32 #include <power/pmic.h>
33 #include <power/pfuze3000_pmic.h>
34 #include <malloc.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 enum {
39 UDOO_NEO_TYPE_BASIC,
40 UDOO_NEO_TYPE_BASIC_KS,
41 UDOO_NEO_TYPE_FULL,
42 UDOO_NEO_TYPE_EXTENDED,
43 };
44
45 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48
49 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
50 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
51 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52
53 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
56 PAD_CTL_ODE)
57
58 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
61
62 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
63 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
64
65 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
66 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
67
68 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
69 PAD_CTL_DSE_40ohm)
70
71 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
73 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
74 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
75 MUX_MODE_SION)
76
dram_init(void)77 int dram_init(void)
78 {
79 gd->ram_size = imx_ddr_size();
80 return 0;
81 }
82
83 #ifdef CONFIG_SYS_I2C_MXC
84 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
85 /* I2C1 for PMIC */
86 static struct i2c_pads_info i2c_pad_info1 = {
87 .scl = {
88 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
89 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
90 .gp = IMX_GPIO_NR(1, 0),
91 },
92 .sda = {
93 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
94 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
95 .gp = IMX_GPIO_NR(1, 1),
96 },
97 };
98 #endif
99
100 #ifdef CONFIG_POWER
power_init_board(void)101 int power_init_board(void)
102 {
103 struct pmic *p;
104 int ret;
105 unsigned int reg, rev_id;
106
107 ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
108 if (ret)
109 return ret;
110
111 p = pmic_get("PFUZE3000");
112 ret = pmic_probe(p);
113 if (ret)
114 return ret;
115
116 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
117 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
118 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
119
120 /* disable Low Power Mode during standby mode */
121 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
122 reg |= 0x1;
123 ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
124 if (ret)
125 return ret;
126
127 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
128 if (ret)
129 return ret;
130
131 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
132 if (ret)
133 return ret;
134
135 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
136 if (ret)
137 return ret;
138
139 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
140 if (ret)
141 return ret;
142
143 /* set SW1A standby voltage 0.975V */
144 pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
145 reg &= ~0x3f;
146 reg |= PFUZE3000_SW1AB_SETP(9750);
147 ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
148 if (ret)
149 return ret;
150
151 /* set SW1B standby voltage 0.975V */
152 pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
153 reg &= ~0x3f;
154 reg |= PFUZE3000_SW1AB_SETP(9750);
155 ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
156 if (ret)
157 return ret;
158
159 /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
160 pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
161 reg &= ~0xc0;
162 reg |= 0x40;
163 ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
164 if (ret)
165 return ret;
166
167 /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
168 pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
169 reg &= ~0xc0;
170 reg |= 0x40;
171 ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
172 if (ret)
173 return ret;
174
175 /* set VDD_ARM_IN to 1.350V */
176 pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
177 reg &= ~0x3f;
178 reg |= PFUZE3000_SW1AB_SETP(13500);
179 ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
180 if (ret)
181 return ret;
182
183 /* set VDD_SOC_IN to 1.350V */
184 pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
185 reg &= ~0x3f;
186 reg |= PFUZE3000_SW1AB_SETP(13500);
187 ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
188 if (ret)
189 return ret;
190
191 /* set DDR_1_5V to 1.350V */
192 pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
193 reg &= ~0x0f;
194 reg |= PFUZE3000_SW3_SETP(13500);
195 ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
196 if (ret)
197 return ret;
198
199 /* set VGEN2_1V5 to 1.5V */
200 pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
201 reg &= ~0x0f;
202 reg |= PFUZE3000_VLDO_SETP(15000);
203 /* enable */
204 reg |= 0x10;
205 ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
206 if (ret)
207 return ret;
208
209 return 0;
210 }
211 #endif
212
213 static iomux_v3_cfg_t const uart1_pads[] = {
214 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
215 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
216 };
217
218 static iomux_v3_cfg_t const usdhc2_pads[] = {
219 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
220 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
221 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
222 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
223 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
224 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
225 /* CD pin */
226 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
227 /* Power */
228 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
229 };
230
231 static iomux_v3_cfg_t const fec1_pads[] = {
232 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
235 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
236 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
237 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
239 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
242 MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
243 MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
244 };
245
246 static iomux_v3_cfg_t const phy_control_pads[] = {
247 /* 25MHz Ethernet PHY Clock */
248 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
249 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
250 };
251
252 static iomux_v3_cfg_t const board_recognition_pads[] = {
253 /*Connected to R184*/
254 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
255 /*Connected to R185*/
256 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
257 };
258
259 static iomux_v3_cfg_t const wdog_b_pad = {
260 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
261 };
262
263 static iomux_v3_cfg_t const peri_3v3_pads[] = {
264 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
265 };
266
setup_iomux_uart(void)267 static void setup_iomux_uart(void)
268 {
269 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
270 }
271
setup_fec(int fec_id)272 static int setup_fec(int fec_id)
273 {
274 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
275 int reg;
276
277 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
278 ARRAY_SIZE(phy_control_pads));
279
280 /* Reset PHY */
281 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
282 udelay(10000);
283 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
284 udelay(100);
285
286 reg = readl(&anatop->pll_enet);
287 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
288 writel(reg, &anatop->pll_enet);
289
290 return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
291 }
292
board_eth_init(bd_t * bis)293 int board_eth_init(bd_t *bis)
294 {
295 uint32_t base = IMX_FEC_BASE;
296 struct mii_dev *bus = NULL;
297 struct phy_device *phydev = NULL;
298 int ret;
299
300 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
301
302 setup_fec(CONFIG_FEC_ENET_DEV);
303
304 bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
305 if (!bus)
306 return -EINVAL;
307
308 phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
309 PHY_INTERFACE_MODE_RMII);
310 if (!phydev) {
311 free(bus);
312 return -EINVAL;
313 }
314
315 ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
316 if (ret) {
317 free(bus);
318 free(phydev);
319 return ret;
320 }
321 return 0;
322 }
323
board_phy_config(struct phy_device * phydev)324 int board_phy_config(struct phy_device *phydev)
325 {
326 if (phydev->drv->config)
327 phydev->drv->config(phydev);
328
329 return 0;
330 }
331
board_init(void)332 int board_init(void)
333 {
334 /* Address of boot parameters */
335 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
336
337 /*
338 * Because kernel set WDOG_B mux before pad with the commone pinctrl
339 * framwork now and wdog reset will be triggered once set WDOG_B mux
340 * with default pad setting, we set pad setting here to workaround this.
341 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
342 * as GPIO mux firstly here to workaround it.
343 */
344 imx_iomux_v3_setup_pad(wdog_b_pad);
345
346 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
347 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
348 ARRAY_SIZE(peri_3v3_pads));
349
350 /* Active high for ncp692 */
351 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
352
353 #ifdef CONFIG_SYS_I2C_MXC
354 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
355 #endif
356
357 return 0;
358 }
359
get_board_value(void)360 static int get_board_value(void)
361 {
362 int r184, r185;
363
364 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
365 ARRAY_SIZE(board_recognition_pads));
366
367 gpio_direction_input(IMX_GPIO_NR(4, 13));
368 gpio_direction_input(IMX_GPIO_NR(4, 0));
369
370 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
371 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
372
373 /*
374 * Machine selection -
375 * Machine r184, r185
376 * ---------------------------------
377 * Basic 0 0
378 * Basic Ks 0 1
379 * Full 1 0
380 * Extended 1 1
381 */
382
383 return (r184 << 1) + r185;
384 }
385
board_early_init_f(void)386 int board_early_init_f(void)
387 {
388 setup_iomux_uart();
389
390 return 0;
391 }
392
393 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
394 {USDHC2_BASE_ADDR, 0, 4},
395 };
396
397 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
398 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
399
board_mmc_getcd(struct mmc * mmc)400 int board_mmc_getcd(struct mmc *mmc)
401 {
402 return !gpio_get_value(USDHC2_CD_GPIO);
403 }
404
board_mmc_init(bd_t * bis)405 int board_mmc_init(bd_t *bis)
406 {
407 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
408 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
409 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
410 gpio_direction_input(USDHC2_CD_GPIO);
411 gpio_direction_output(USDHC2_PWR_GPIO, 1);
412
413 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
414 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
415 }
416
board_string(void)417 static char *board_string(void)
418 {
419 switch (get_board_value()) {
420 case UDOO_NEO_TYPE_BASIC:
421 return "BASIC";
422 case UDOO_NEO_TYPE_BASIC_KS:
423 return "BASICKS";
424 case UDOO_NEO_TYPE_FULL:
425 return "FULL";
426 case UDOO_NEO_TYPE_EXTENDED:
427 return "EXTENDED";
428 }
429 return "UNDEFINED";
430 }
431
checkboard(void)432 int checkboard(void)
433 {
434 printf("Board: UDOO Neo %s\n", board_string());
435 return 0;
436 }
437
board_late_init(void)438 int board_late_init(void)
439 {
440 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
441 env_set("board_name", board_string());
442 #endif
443
444 return 0;
445 }
446
447 #ifdef CONFIG_SPL_BUILD
448
449 #include <linux/libfdt.h>
450 #include <asm/arch/mx6-ddr.h>
451
452 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
453 .dram_dqm0 = 0x00000028,
454 .dram_dqm1 = 0x00000028,
455 .dram_dqm2 = 0x00000028,
456 .dram_dqm3 = 0x00000028,
457 .dram_ras = 0x00000020,
458 .dram_cas = 0x00000020,
459 .dram_odt0 = 0x00000020,
460 .dram_odt1 = 0x00000020,
461 .dram_sdba2 = 0x00000000,
462 .dram_sdcke0 = 0x00003000,
463 .dram_sdcke1 = 0x00003000,
464 .dram_sdclk_0 = 0x00000030,
465 .dram_sdqs0 = 0x00000028,
466 .dram_sdqs1 = 0x00000028,
467 .dram_sdqs2 = 0x00000028,
468 .dram_sdqs3 = 0x00000028,
469 .dram_reset = 0x00000020,
470 };
471
472 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
473 .grp_addds = 0x00000020,
474 .grp_ddrmode_ctl = 0x00020000,
475 .grp_ddrpke = 0x00000000,
476 .grp_ddrmode = 0x00020000,
477 .grp_b0ds = 0x00000028,
478 .grp_b1ds = 0x00000028,
479 .grp_ctlds = 0x00000020,
480 .grp_ddr_type = 0x000c0000,
481 .grp_b2ds = 0x00000028,
482 .grp_b3ds = 0x00000028,
483 };
484
485 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
486 .p0_mpwldectrl0 = 0x000E000B,
487 .p0_mpwldectrl1 = 0x000E0010,
488 .p0_mpdgctrl0 = 0x41600158,
489 .p0_mpdgctrl1 = 0x01500140,
490 .p0_mprddlctl = 0x3A383E3E,
491 .p0_mpwrdlctl = 0x3A383C38,
492 };
493
494 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
495 .p0_mpwldectrl0 = 0x001E0022,
496 .p0_mpwldectrl1 = 0x001C0019,
497 .p0_mpdgctrl0 = 0x41540150,
498 .p0_mpdgctrl1 = 0x01440138,
499 .p0_mprddlctl = 0x403E4644,
500 .p0_mpwrdlctl = 0x3C3A4038,
501 };
502
503 /* MT41K256M16 */
504 static struct mx6_ddr3_cfg neo_mem_ddr = {
505 .mem_speed = 1600,
506 .density = 4,
507 .width = 16,
508 .banks = 8,
509 .rowaddr = 15,
510 .coladdr = 10,
511 .pagesz = 2,
512 .trcd = 1375,
513 .trcmin = 4875,
514 .trasmin = 3500,
515 };
516
517 /* MT41K128M16 */
518 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
519 .mem_speed = 1600,
520 .density = 2,
521 .width = 16,
522 .banks = 8,
523 .rowaddr = 14,
524 .coladdr = 10,
525 .pagesz = 2,
526 .trcd = 1375,
527 .trcmin = 4875,
528 .trasmin = 3500,
529 };
530
ccgr_init(void)531 static void ccgr_init(void)
532 {
533 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
534
535 writel(0xFFFFFFFF, &ccm->CCGR0);
536 writel(0xFFFFFFFF, &ccm->CCGR1);
537 writel(0xFFFFFFFF, &ccm->CCGR2);
538 writel(0xFFFFFFFF, &ccm->CCGR3);
539 writel(0xFFFFFFFF, &ccm->CCGR4);
540 writel(0xFFFFFFFF, &ccm->CCGR5);
541 writel(0xFFFFFFFF, &ccm->CCGR6);
542 writel(0xFFFFFFFF, &ccm->CCGR7);
543 }
544
spl_dram_init(void)545 static void spl_dram_init(void)
546 {
547 int board = get_board_value();
548
549 struct mx6_ddr_sysinfo sysinfo = {
550 .dsize = 1, /* width of data bus: 1 = 32 bits */
551 .cs_density = 24,
552 .ncs = 1,
553 .cs1_mirror = 0,
554 .rtt_wr = 2,
555 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
556 .walat = 1, /* Write additional latency */
557 .ralat = 5, /* Read additional latency */
558 .mif3_mode = 3, /* Command prediction working mode */
559 .bi_on = 1, /* Bank interleaving enabled */
560 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
561 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
562 };
563
564 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
565 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
566 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
567 &neo_basic_mem_ddr);
568 else
569 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
570 }
571
board_init_f(ulong dummy)572 void board_init_f(ulong dummy)
573 {
574 ccgr_init();
575
576 /* setup AIPS and disable watchdog */
577 arch_cpu_init();
578
579 board_early_init_f();
580
581 /* setup GP timer */
582 timer_init();
583
584 /* UART clocks enabled and gd valid - init serial console */
585 preloader_console_init();
586
587 /* DDR initialization */
588 spl_dram_init();
589
590 /* Clear the BSS. */
591 memset(__bss_start, 0, __bss_end - __bss_start);
592
593 /* load/boot image from boot device */
594 board_init_r(NULL, 0);
595 }
596
597 #endif
598