1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <init.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <env.h>
13 #include <malloc.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <linux/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/sata.h>
19 #include <mmc.h>
20 #include <fsl_esdhc_imx.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/io.h>
23 #include <asm/arch/sys_proto.h>
24 #include <micrel.h>
25 #include <miiphy.h>
26 #include <netdev.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
32 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33
34 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
36
37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41 #define WDT_EN IMX_GPIO_NR(5, 4)
42 #define WDT_TRG IMX_GPIO_NR(3, 19)
43
dram_init(void)44 int dram_init(void)
45 {
46 gd->ram_size = imx_ddr_size();
47
48 return 0;
49 }
50
51 static iomux_v3_cfg_t const uart2_pads[] = {
52 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
53 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
54 };
55
56 static iomux_v3_cfg_t const usdhc3_pads[] = {
57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 };
64
65 static iomux_v3_cfg_t const wdog_pads[] = {
66 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
67 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
68 };
69
mx6_rgmii_rework(struct phy_device * phydev)70 int mx6_rgmii_rework(struct phy_device *phydev)
71 {
72 /*
73 * Bug: Apparently uDoo does not works with Gigabit switches...
74 * Limiting speed to 10/100Mbps, and setting master mode, seems to
75 * be the only way to have a successfull PHY auto negotiation.
76 * How to fix: Understand why Linux kernel do not have this issue.
77 */
78 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
79
80 /* control data pad skew - devaddr = 0x02, register = 0x04 */
81 ksz9031_phy_extended_write(phydev, 0x02,
82 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
83 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
84 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
85 ksz9031_phy_extended_write(phydev, 0x02,
86 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
87 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
88 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
89 ksz9031_phy_extended_write(phydev, 0x02,
90 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
91 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
92 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
93 ksz9031_phy_extended_write(phydev, 0x02,
94 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
95 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
96 return 0;
97 }
98
99 static iomux_v3_cfg_t const enet_pads1[] = {
100 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
108 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
110 /* RGMII reset */
111 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 /* Ethernet power supply */
113 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 /* pin 32 - 1 - (MODE0) all */
115 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
116 /* pin 31 - 1 - (MODE1) all */
117 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 /* pin 28 - 1 - (MODE2) all */
119 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
120 /* pin 27 - 1 - (MODE3) all */
121 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
122 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
123 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
124 };
125
126 static iomux_v3_cfg_t const enet_pads2[] = {
127 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
130 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
131 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
132 };
133
setup_iomux_enet(void)134 static void setup_iomux_enet(void)
135 {
136 SETUP_IOMUX_PADS(enet_pads1);
137 udelay(20);
138 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
139
140 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
141
142 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
143 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
144 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
145 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
146 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
147 udelay(1000);
148
149 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
150
151 /* Need 100ms delay to exit from reset. */
152 udelay(1000 * 100);
153
154 gpio_free(IMX_GPIO_NR(6, 24));
155 gpio_free(IMX_GPIO_NR(6, 25));
156 gpio_free(IMX_GPIO_NR(6, 27));
157 gpio_free(IMX_GPIO_NR(6, 28));
158 gpio_free(IMX_GPIO_NR(6, 29));
159
160 SETUP_IOMUX_PADS(enet_pads2);
161 }
162
setup_iomux_uart(void)163 static void setup_iomux_uart(void)
164 {
165 SETUP_IOMUX_PADS(uart2_pads);
166 }
167
setup_iomux_wdog(void)168 static void setup_iomux_wdog(void)
169 {
170 SETUP_IOMUX_PADS(wdog_pads);
171 gpio_direction_output(WDT_TRG, 0);
172 gpio_direction_output(WDT_EN, 1);
173 gpio_direction_input(WDT_TRG);
174 }
175
176 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
177
board_mmc_getcd(struct mmc * mmc)178 int board_mmc_getcd(struct mmc *mmc)
179 {
180 return 1; /* Always present */
181 }
182
board_eth_init(bd_t * bis)183 int board_eth_init(bd_t *bis)
184 {
185 uint32_t base = IMX_FEC_BASE;
186 struct mii_dev *bus = NULL;
187 struct phy_device *phydev = NULL;
188 int ret;
189
190 setup_iomux_enet();
191
192 #ifdef CONFIG_FEC_MXC
193 bus = fec_get_miibus(base, -1);
194 if (!bus)
195 return -EINVAL;
196 /* scan phy 4,5,6,7 */
197 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
198
199 if (!phydev) {
200 ret = -EINVAL;
201 goto free_bus;
202 }
203 printf("using phy at %d\n", phydev->addr);
204 ret = fec_probe(bis, -1, base, bus, phydev);
205 if (ret)
206 goto free_phydev;
207 #endif
208 return 0;
209
210 free_phydev:
211 free(phydev);
212 free_bus:
213 free(bus);
214 return ret;
215 }
216
board_mmc_init(bd_t * bis)217 int board_mmc_init(bd_t *bis)
218 {
219 SETUP_IOMUX_PADS(usdhc3_pads);
220 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
221 usdhc_cfg.max_bus_width = 4;
222
223 return fsl_esdhc_initialize(bis, &usdhc_cfg);
224 }
225
board_early_init_f(void)226 int board_early_init_f(void)
227 {
228 setup_iomux_wdog();
229 setup_iomux_uart();
230
231 return 0;
232 }
233
board_phy_config(struct phy_device * phydev)234 int board_phy_config(struct phy_device *phydev)
235 {
236 mx6_rgmii_rework(phydev);
237 if (phydev->drv->config)
238 phydev->drv->config(phydev);
239
240 return 0;
241 }
242
board_init(void)243 int board_init(void)
244 {
245 /* address of boot parameters */
246 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
247
248 #ifdef CONFIG_SATA
249 setup_sata();
250 #endif
251 return 0;
252 }
253
board_late_init(void)254 int board_late_init(void)
255 {
256 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
257 if (is_cpu_type(MXC_CPU_MX6Q))
258 env_set("board_rev", "MX6Q");
259 else
260 env_set("board_rev", "MX6DL");
261 #endif
262 return 0;
263 }
264
checkboard(void)265 int checkboard(void)
266 {
267 if (is_cpu_type(MXC_CPU_MX6Q))
268 puts("Board: Udoo Quad\n");
269 else
270 puts("Board: Udoo DualLite\n");
271
272 return 0;
273 }
274