1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2019 Variscite Ltd.
4 * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/iomux-v3.h>
12 #include <asm/mach-imx/mxc_i2c.h>
13 #include <fsl_esdhc_imx.h>
14 #include <linux/bitops.h>
15 #include <miiphy.h>
16 #include <netdev.h>
17 #include <usb.h>
18 #include <usb/ehci-ci.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
dram_init(void)22 int dram_init(void)
23 {
24 gd->ram_size = imx_ddr_size();
25
26 return 0;
27 }
28
29 #ifdef CONFIG_NAND_MXS
30 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
31 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
32 PAD_CTL_SRE_FAST)
33 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
34 static iomux_v3_cfg_t const nand_pads[] = {
35 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
36 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
37 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
38 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
39 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
40 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
41 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
42 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
43 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
44 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
45 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
46 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
47 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
48 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
49 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
50 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
51 };
52
setup_gpmi_nand(void)53 static void setup_gpmi_nand(void)
54 {
55 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
56
57 /* config gpmi nand iomux */
58 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
59
60 clrbits_le32(&mxc_ccm->CCGR4,
61 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
64 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
65 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
66
67 /*
68 * config gpmi and bch clock to 100 MHz
69 * bch/gpmi select PLL2 PFD2 400M
70 * 100M = 400M / 4
71 */
72 clrbits_le32(&mxc_ccm->cscmr1,
73 MXC_CCM_CSCMR1_BCH_CLK_SEL |
74 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
75 clrsetbits_le32(&mxc_ccm->cscdr1,
76 MXC_CCM_CSCDR1_BCH_PODF_MASK |
77 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
78 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
79 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
80
81 /* enable gpmi and bch clock gating */
82 setbits_le32(&mxc_ccm->CCGR4,
83 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
84 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
87 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
88
89 /* enable apbh clock gating */
90 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
91 }
92 #endif
93
94 #ifdef CONFIG_FEC_MXC
95 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
96 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
97 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
98 PAD_CTL_SRE_FAST)
99 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
100 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
101 PAD_CTL_ODE)
102 /*
103 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
104 * be used for ENET1 or ENET2, cannot be used for both.
105 */
106 static iomux_v3_cfg_t const fec1_pads[] = {
107 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
108 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
113 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 };
118
119 static iomux_v3_cfg_t const fec2_pads[] = {
120 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
121 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
126 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
128 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 };
131
setup_iomux_fec(int fec_id)132 static void setup_iomux_fec(int fec_id)
133 {
134 if (fec_id == 0)
135 imx_iomux_v3_setup_multiple_pads(fec1_pads,
136 ARRAY_SIZE(fec1_pads));
137 else
138 imx_iomux_v3_setup_multiple_pads(fec2_pads,
139 ARRAY_SIZE(fec2_pads));
140 }
141
board_eth_init(bd_t * bis)142 int board_eth_init(bd_t *bis)
143 {
144 int ret = 0;
145
146 ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
147 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
148
149 #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
150 /* USB Ethernet Gadget */
151 usb_eth_initialize(bis);
152 #endif
153 return ret;
154 }
155
setup_fec(int fec_id)156 static int setup_fec(int fec_id)
157 {
158 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
159 int ret;
160
161 if (fec_id == 0) {
162 /*
163 * Use 50M anatop loopback REF_CLK1 for ENET1,
164 * clear gpr1[13], set gpr1[17].
165 */
166 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
167 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
168 } else {
169 /*
170 * Use 50M anatop loopback REF_CLK2 for ENET2,
171 * clear gpr1[14], set gpr1[18].
172 */
173 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
174 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
175 }
176
177 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
178 if (ret)
179 return ret;
180
181 enable_enet_clk(1);
182
183 return 0;
184 }
185
board_phy_config(struct phy_device * phydev)186 int board_phy_config(struct phy_device *phydev)
187 {
188 /*
189 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
190 * 50 MHz RMII clock mode.
191 */
192 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
193
194 if (phydev->drv->config)
195 phydev->drv->config(phydev);
196
197 return 0;
198 }
199 #endif /* CONFIG_FEC_MXC */
200
board_early_init_f(void)201 int board_early_init_f(void)
202 {
203 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
204
205 return 0;
206 }
207
board_init(void)208 int board_init(void)
209 {
210 /* Address of boot parameters */
211 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
212
213 #ifdef CONFIG_FEC_MXC
214 setup_fec(CONFIG_FEC_ENET_DEV);
215 #endif
216
217 #ifdef CONFIG_NAND_MXS
218 setup_gpmi_nand();
219 #endif
220 return 0;
221 }
222
checkboard(void)223 int checkboard(void)
224 {
225 puts("Board: Variscite DART-6UL Evaluation Kit\n");
226
227 return 0;
228 }
229