1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Wandboard
4 * Author: Tungyi Lin <tungyilin1127@gmail.com>
5 * Richard Hu <hakahu@gmail.com>
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <linux/errno.h>
13 #include <asm/gpio.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/video.h>
16 #include <mmc.h>
17 #include <fsl_esdhc_imx.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/io.h>
20 #include <asm/arch/sys_proto.h>
21 #include <spl.h>
22
23 #include <asm/arch/mx6-ddr.h>
24 /*
25 * Driving strength:
26 * 0x30 == 40 Ohm
27 * 0x28 == 48 Ohm
28 */
29
30 #define IMX6DQ_DRIVE_STRENGTH 0x30
31 #define IMX6SDL_DRIVE_STRENGTH 0x28
32 #define IMX6QP_DRIVE_STRENGTH 0x28
33
34 /* configure MX6Q/DUAL mmdc DDR io registers */
35 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
36 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
37 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
38 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
39 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
40 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
41 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
42 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
43 .dram_sdba2 = 0x00000000,
44 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
45 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
46 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
47 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
48 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
49 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
50 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
51 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
52 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
53 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
54 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
55 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
56 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
57 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
58 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
59 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
60 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
61 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
62 };
63
64 /* configure MX6QP mmdc DDR io registers */
65 static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
66 .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
67 .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
68 .dram_cas = IMX6QP_DRIVE_STRENGTH,
69 .dram_ras = IMX6QP_DRIVE_STRENGTH,
70 .dram_reset = IMX6QP_DRIVE_STRENGTH,
71 .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
72 .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
73 .dram_sdba2 = 0x00000000,
74 .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
75 .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
76 .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
77 .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
78 .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
79 .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
80 .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
81 .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
82 .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
83 .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
84 .dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
85 .dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
86 .dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
87 .dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
88 .dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
89 .dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
90 .dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
91 .dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
92 };
93
94 /* configure MX6Q/DUAL mmdc GRP io registers */
95 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
96 .grp_ddr_type = 0x000c0000,
97 .grp_ddrmode_ctl = 0x00020000,
98 .grp_ddrpke = 0x00000000,
99 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
100 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
101 .grp_ddrmode = 0x00020000,
102 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
103 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
104 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
105 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
106 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
107 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
108 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
109 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
110 };
111
112 /* configure MX6QP mmdc GRP io registers */
113 static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
114 .grp_ddr_type = 0x000c0000,
115 .grp_ddrmode_ctl = 0x00020000,
116 .grp_ddrpke = 0x00000000,
117 .grp_addds = IMX6QP_DRIVE_STRENGTH,
118 .grp_ctlds = IMX6QP_DRIVE_STRENGTH,
119 .grp_ddrmode = 0x00020000,
120 .grp_b0ds = IMX6QP_DRIVE_STRENGTH,
121 .grp_b1ds = IMX6QP_DRIVE_STRENGTH,
122 .grp_b2ds = IMX6QP_DRIVE_STRENGTH,
123 .grp_b3ds = IMX6QP_DRIVE_STRENGTH,
124 .grp_b4ds = IMX6QP_DRIVE_STRENGTH,
125 .grp_b5ds = IMX6QP_DRIVE_STRENGTH,
126 .grp_b6ds = IMX6QP_DRIVE_STRENGTH,
127 .grp_b7ds = IMX6QP_DRIVE_STRENGTH,
128 };
129
130 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
131 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
132 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
133 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
134 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
135 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
136 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
137 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
138 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
139 .dram_sdba2 = 0x00000000,
140 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
141 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
142 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
143 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
144 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
145 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
146 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
147 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
148 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
149 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
150 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
151 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
152 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
153 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
154 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
155 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
156 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
157 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
158 };
159
160 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
161 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
162 .grp_ddr_type = 0x000c0000,
163 .grp_ddrmode_ctl = 0x00020000,
164 .grp_ddrpke = 0x00000000,
165 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
166 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
167 .grp_ddrmode = 0x00020000,
168 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
169 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
170 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
171 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
172 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
173 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
174 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
175 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
176 };
177
178 /* H5T04G63AFR-PB */
179 static struct mx6_ddr3_cfg h5t04g63afr = {
180 .mem_speed = 1600,
181 .density = 4,
182 .width = 16,
183 .banks = 8,
184 .rowaddr = 15,
185 .coladdr = 10,
186 .pagesz = 2,
187 .trcd = 1375,
188 .trcmin = 4875,
189 .trasmin = 3500,
190 };
191
192 /* H5TQ2G63DFR-H9 */
193 static struct mx6_ddr3_cfg h5tq2g63dfr = {
194 .mem_speed = 1333,
195 .density = 2,
196 .width = 16,
197 .banks = 8,
198 .rowaddr = 14,
199 .coladdr = 10,
200 .pagesz = 2,
201 .trcd = 1350,
202 .trcmin = 4950,
203 .trasmin = 3600,
204 };
205
206 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
207 .p0_mpwldectrl0 = 0x001f001f,
208 .p0_mpwldectrl1 = 0x001f001f,
209 .p1_mpwldectrl0 = 0x001f001f,
210 .p1_mpwldectrl1 = 0x001f001f,
211 .p0_mpdgctrl0 = 0x4301030d,
212 .p0_mpdgctrl1 = 0x03020277,
213 .p1_mpdgctrl0 = 0x4300030a,
214 .p1_mpdgctrl1 = 0x02780248,
215 .p0_mprddlctl = 0x4536393b,
216 .p1_mprddlctl = 0x36353441,
217 .p0_mpwrdlctl = 0x41414743,
218 .p1_mpwrdlctl = 0x462f453f,
219 };
220
221 /* DDR 64bit 2GB */
222 static struct mx6_ddr_sysinfo mem_q = {
223 .dsize = 2,
224 .cs1_mirror = 0,
225 /* config for full 4GB range so that get_mem_size() works */
226 .cs_density = 32,
227 .ncs = 1,
228 .bi_on = 1,
229 .rtt_nom = 1,
230 .rtt_wr = 0,
231 .ralat = 5,
232 .walat = 0,
233 .mif3_mode = 3,
234 .rst_to_cke = 0x23,
235 .sde_to_rst = 0x10,
236 .refsel = 1, /* Refresh cycles at 32KHz */
237 .refr = 3, /* 4 refresh commands per refresh cycle */
238 };
239
240 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
241 .p0_mpwldectrl0 = 0x001f001f,
242 .p0_mpwldectrl1 = 0x001f001f,
243 .p1_mpwldectrl0 = 0x001f001f,
244 .p1_mpwldectrl1 = 0x001f001f,
245 .p0_mpdgctrl0 = 0x420e020e,
246 .p0_mpdgctrl1 = 0x02000200,
247 .p1_mpdgctrl0 = 0x42020202,
248 .p1_mpdgctrl1 = 0x01720172,
249 .p0_mprddlctl = 0x494c4f4c,
250 .p1_mprddlctl = 0x4a4c4c49,
251 .p0_mpwrdlctl = 0x3f3f3133,
252 .p1_mpwrdlctl = 0x39373f2e,
253 };
254
255 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
256 .p0_mpwldectrl0 = 0x0040003c,
257 .p0_mpwldectrl1 = 0x0032003e,
258 .p0_mpdgctrl0 = 0x42350231,
259 .p0_mpdgctrl1 = 0x021a0218,
260 .p0_mprddlctl = 0x4b4b4e49,
261 .p0_mpwrdlctl = 0x3f3f3035,
262 };
263
264 /* DDR 64bit 1GB */
265 static struct mx6_ddr_sysinfo mem_dl = {
266 .dsize = 2,
267 .cs1_mirror = 0,
268 /* config for full 4GB range so that get_mem_size() works */
269 .cs_density = 32,
270 .ncs = 1,
271 .bi_on = 1,
272 .rtt_nom = 1,
273 .rtt_wr = 0,
274 .ralat = 5,
275 .walat = 0,
276 .mif3_mode = 3,
277 .rst_to_cke = 0x23,
278 .sde_to_rst = 0x10,
279 .refsel = 1, /* Refresh cycles at 32KHz */
280 .refr = 3, /* 4 refresh commands per refresh cycle */
281 };
282
283 /* DDR 32bit 512MB */
284 static struct mx6_ddr_sysinfo mem_s = {
285 .dsize = 1,
286 .cs1_mirror = 0,
287 /* config for full 4GB range so that get_mem_size() works */
288 .cs_density = 32,
289 .ncs = 1,
290 .bi_on = 1,
291 .rtt_nom = 1,
292 .rtt_wr = 0,
293 .ralat = 5,
294 .walat = 0,
295 .mif3_mode = 3,
296 .rst_to_cke = 0x23,
297 .sde_to_rst = 0x10,
298 .refsel = 1, /* Refresh cycles at 32KHz */
299 .refr = 3, /* 4 refresh commands per refresh cycle */
300 };
301
ccgr_init(void)302 static void ccgr_init(void)
303 {
304 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
305
306 writel(0x00C03F3F, &ccm->CCGR0);
307 writel(0x0030FC03, &ccm->CCGR1);
308 writel(0x0FFFC000, &ccm->CCGR2);
309 writel(0x3FF03000, &ccm->CCGR3);
310 writel(0x00FFF300, &ccm->CCGR4);
311 writel(0x0F0000C3, &ccm->CCGR5);
312 writel(0x000003FF, &ccm->CCGR6);
313 }
314
spl_dram_init_imx6qp_lpddr3(void)315 static void spl_dram_init_imx6qp_lpddr3(void)
316 {
317 /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
318 writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
319 /* Calibrations - ZQ */
320 writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
321 /* write leveling */
322 writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
323 writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
324 writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
325 writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
326 /*
327 * DQS gating, read delay, write delay calibration values
328 * based on calibration compare of 0x00ffff00
329 */
330 writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
331 writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
332 writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
333 writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
334 writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
335 writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
336 writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
337 writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
338 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
339 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
340 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
341 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
342 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
343 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
344 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
345 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
346 writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
347 writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
348 writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
349 writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
350 /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
351 writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
352 writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
353 writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
354 writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
355 writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
356 writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
357 writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
358 writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
359 writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
360 writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
361 writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
362 writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
363 writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
364 /* add NOC DDR configuration */
365 writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
366 writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
367 writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
368 writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
369 writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
370 writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
371 writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
372 writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
373 writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
374 writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
375 writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
376 writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
377 writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
378 writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
379 writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
380 writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
381 writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
382 }
383
spl_dram_init(void)384 static void spl_dram_init(void)
385 {
386 if (is_mx6dqp()) {
387 mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
388 spl_dram_init_imx6qp_lpddr3();
389 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
390 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
391 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
392 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
393 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
394 mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
395 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
396 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
397 mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
398 }
399
400 udelay(100);
401 }
402
board_init_f(ulong dummy)403 void board_init_f(ulong dummy)
404 {
405 ccgr_init();
406
407 /* setup AIPS and disable watchdog */
408 arch_cpu_init();
409
410 gpr_init();
411
412 /* iomux */
413 board_early_init_f();
414
415 /* setup GP timer */
416 timer_init();
417
418 /* UART clocks enabled and gd valid - init serial console */
419 preloader_console_init();
420
421 /* DDR initialization */
422 spl_dram_init();
423 }
424
425 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
426 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
427
428 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
429 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
430 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
431
432 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
433 {USDHC3_BASE_ADDR},
434 {USDHC1_BASE_ADDR},
435 };
436
437 static iomux_v3_cfg_t const usdhc1_pads[] = {
438 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
439 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
440 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
441 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
442 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
443 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
444 /* Carrier MicroSD Card Detect */
445 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
446 };
447
448 static iomux_v3_cfg_t const usdhc3_pads[] = {
449 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
450 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
451 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
452 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
453 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
454 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
455 /* SOM MicroSD Card Detect */
456 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
457 };
458
board_mmc_getcd(struct mmc * mmc)459 int board_mmc_getcd(struct mmc *mmc)
460 {
461 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
462 int ret = 0;
463
464 switch (cfg->esdhc_base) {
465 case USDHC1_BASE_ADDR:
466 ret = !gpio_get_value(USDHC1_CD_GPIO);
467 break;
468 case USDHC3_BASE_ADDR:
469 ret = !gpio_get_value(USDHC3_CD_GPIO);
470 break;
471 }
472
473 return ret;
474 }
475
board_mmc_init(bd_t * bis)476 int board_mmc_init(bd_t *bis)
477 {
478 int ret;
479 u32 index = 0;
480
481 /*
482 * Following map is done:
483 * (U-Boot device node) (Physical Port)
484 * mmc0 SOM MicroSD
485 * mmc1 Carrier board MicroSD
486 */
487 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
488 switch (index) {
489 case 0:
490 SETUP_IOMUX_PADS(usdhc3_pads);
491 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
492 usdhc_cfg[0].max_bus_width = 4;
493 gpio_direction_input(USDHC3_CD_GPIO);
494 break;
495 case 1:
496 SETUP_IOMUX_PADS(usdhc1_pads);
497 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
498 usdhc_cfg[1].max_bus_width = 4;
499 gpio_direction_input(USDHC1_CD_GPIO);
500 break;
501 default:
502 printf("Warning: you configured more USDHC controllers"
503 "(%d) then supported by the board (%d)\n",
504 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
505 return -EINVAL;
506 }
507
508 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
509 if (ret)
510 return ret;
511 }
512
513 return 0;
514 }
515