1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * Copyright 2008 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <i2c.h>
9
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12
get_spd(ddr2_spd_eeprom_t * spd,u8 i2c_address)13 void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
14 {
15 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
16 sizeof(ddr2_spd_eeprom_t));
17 }
18
19 /*
20 * There are four board-specific SDRAM timing parameters which must be
21 * calculated based on the particular PCB artwork. These are:
22 * 1.) CPO (Read Capture Delay)
23 * - TIMING_CFG_2 register
24 * Source: Calculation based on board trace lengths and
25 * chip-specific internal delays.
26 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27 * - TIMING_CFG_2 register
28 * Source: Calculation based on board trace lengths.
29 * Unless clock and DQ lanes are very different
30 * lengths (>2"), this should be set to the nominal value
31 * of 1/2 clock delay.
32 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
33 * - DDR_SDRAM_CLK_CNTL register
34 * Source: Signal Integrity Simulations
35 * 4.) 2T Timing on Addr/Ctl
36 * - TIMING_CFG_2 register
37 * Source: Signal Integrity Simulations
38 * Usually only needed with heavy load/very high speed (>DDR2-800)
39 *
40 * ====== XPedite5370 DDR2-600 read delay calculations ======
41 *
42 * See Freescale's App Note AN2583 as refrence. This document also
43 * contains the chip-specific delays for 8548E, 8572, etc.
44 *
45 * For MPC8572E
46 * Minimum chip delay (Ch 0): 1.372ns
47 * Maximum chip delay (Ch 0): 2.914ns
48 * Minimum chip delay (Ch 1): 1.220ns
49 * Maximum chip delay (Ch 1): 2.595ns
50 *
51 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
52 *
53 * Minimum delay calc (Ch 0):
54 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
55 * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
56 * = 3808ps
57 * = 3.808ns
58 *
59 * Maximum delay calc (Ch 0):
60 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
61 * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
62 * = 6240ps
63 * = 6.240ns
64 *
65 * Minimum delay calc (Ch 1):
66 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
67 * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
68 * = 3288ps
69 * = 3.288ns
70 *
71 * Maximum delay calc (Ch 1):
72 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
73 * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
74 * = 5536ps
75 * = 5.536ns
76 *
77 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
78 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
79 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
80 * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
81 *
82 *
83 * ====== XPedite5370 DDR2-800 read delay calculations ======
84 *
85 * See Freescale's App Note AN2583 as refrence. This document also
86 * contains the chip-specific delays for 8548E, 8572, etc.
87 *
88 * For MPC8572E
89 * Minimum chip delay (Ch 0): 1.372ns
90 * Maximum chip delay (Ch 0): 2.914ns
91 * Minimum chip delay (Ch 1): 1.220ns
92 * Maximum chip delay (Ch 1): 2.595ns
93 *
94 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
95 *
96 * Minimum delay calc (Ch 0):
97 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
98 * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
99 * = 3341ps
100 * = 3.341ns
101 *
102 * Maximum delay calc (Ch 0):
103 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
104 * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
105 * = 5673ps
106 * = 5.673ns
107 *
108 * Minimum delay calc (Ch 1):
109 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
110 * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
111 * = 2822ps
112 * = 2.822ns
113 *
114 * Maximum delay calc (Ch 1):
115 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
116 * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
117 * = 4968ps
118 * = 4.968ns
119 *
120 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
121 * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
122 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
123 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
124 *
125 * Write latency (WR_DATA_DELAY) is calculated by doing the following:
126 *
127 * The DDR SDRAM specification requires DQS be received no sooner than
128 * 75% of an SDRAM clock period—and no later than 125% of a clock
129 * period—from the capturing clock edge of the command/address at the
130 * SDRAM.
131 *
132 * Based on the above tracelengths, the following are calculated:
133 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
134 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
135 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
136 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
137 *
138 * Difference in arrival time CLK vs. DQS:
139 * Ch. 0 0.072ns
140 * Ch. 1 0.138ns
141 *
142 * Both of these values are much less than 25% of the clock
143 * period at DDR2-600 or DDR2-800, so no additional delay is needed over
144 * the 1/2 cycle which normally aligns the first DQS transition
145 * exactly WL (CAS latency minus one cycle) after the CAS strobe.
146 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
147 * terminology corresponds to exactly one clock period delay after
148 * the CAS strobe. (due to the fact that the "delay" is referenced
149 * from the *falling* edge of the CLK, just after the rising edge
150 * which the CAS strobe is latched on.
151 */
152
153 typedef struct board_memctl_options {
154 uint16_t datarate_mhz_low;
155 uint16_t datarate_mhz_high;
156 uint8_t clk_adjust;
157 uint8_t cpo_override;
158 uint8_t write_data_delay;
159 } board_memctl_options_t;
160
161 static struct board_memctl_options bopts_ctrl[][2] = {
162 {
163 /* Controller 0 */
164 {
165 /* DDR2 600/667 */
166 .datarate_mhz_low = 500,
167 .datarate_mhz_high = 750,
168 .clk_adjust = 5,
169 .cpo_override = 8,
170 .write_data_delay = 2,
171 },
172 {
173 /* DDR2 800 */
174 .datarate_mhz_low = 750,
175 .datarate_mhz_high = 850,
176 .clk_adjust = 5,
177 .cpo_override = 9,
178 .write_data_delay = 2,
179 },
180 },
181 {
182 /* Controller 1 */
183 {
184 /* DDR2 600/667 */
185 .datarate_mhz_low = 500,
186 .datarate_mhz_high = 750,
187 .clk_adjust = 5,
188 .cpo_override = 7,
189 .write_data_delay = 2,
190 },
191 {
192 /* DDR2 800 */
193 .datarate_mhz_low = 750,
194 .datarate_mhz_high = 850,
195 .clk_adjust = 5,
196 .cpo_override = 8,
197 .write_data_delay = 2,
198 },
199 },
200 };
201
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)202 void fsl_ddr_board_options(memctl_options_t *popts,
203 dimm_params_t *pdimm,
204 unsigned int ctrl_num)
205 {
206 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
207 sys_info_t sysinfo;
208 int i;
209 unsigned int datarate;
210
211 get_sys_info(&sysinfo);
212 datarate = sysinfo.freq_ddrbus / 1000 / 1000;
213
214 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
215 if ((bopts[i].datarate_mhz_low <= datarate) &&
216 (bopts[i].datarate_mhz_high >= datarate)) {
217 debug("controller %d:\n", ctrl_num);
218 debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
219 debug(" cpo = %d\n", bopts[i].cpo_override);
220 debug(" write_data_delay = %d\n",
221 bopts[i].write_data_delay);
222 popts->clk_adjust = bopts[i].clk_adjust;
223 popts->cpo_override = bopts[i].cpo_override;
224 popts->write_data_delay = bopts[i].write_data_delay;
225 }
226 }
227
228 /*
229 * Factors to consider for half-strength driver enable:
230 * - number of DIMMs installed
231 */
232 popts->half_strength_driver_enable = 0;
233 }
234