1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
4 */
5 #include <common.h>
6 #include <command.h>
7 #include <dm.h>
8
9 #include <asm/io.h>
10 #include <asm/pl310.h>
11
l2c310_of_parse_and_init(struct udevice * dev)12 static void l2c310_of_parse_and_init(struct udevice *dev)
13 {
14 u32 tag[3] = { 0, 0, 0 };
15 u32 saved_reg, prefetch;
16 struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
17
18 /* Disable the L2 Cache */
19 clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
20
21 saved_reg = readl(®s->pl310_aux_ctrl);
22 if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
23 if (prefetch)
24 saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
25 else
26 saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
27 }
28
29 if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
30 if (prefetch)
31 saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
32 else
33 saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
34 }
35
36 saved_reg |= dev_read_bool(dev, "arm,shared-override");
37 writel(saved_reg, ®s->pl310_aux_ctrl);
38
39 saved_reg = readl(®s->pl310_tag_latency_ctrl);
40 if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
41 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
42 L310_LATENCY_CTRL_WR(tag[1] - 1) |
43 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
44 writel(saved_reg, ®s->pl310_tag_latency_ctrl);
45
46 saved_reg = readl(®s->pl310_data_latency_ctrl);
47 if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
48 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
49 L310_LATENCY_CTRL_WR(tag[1] - 1) |
50 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
51 writel(saved_reg, ®s->pl310_data_latency_ctrl);
52
53 /* Enable the L2 cache */
54 setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
55 }
56
l2x0_probe(struct udevice * dev)57 static int l2x0_probe(struct udevice *dev)
58 {
59 l2c310_of_parse_and_init(dev);
60
61 return 0;
62 }
63
64
65 static const struct udevice_id l2x0_ids[] = {
66 { .compatible = "arm,pl310-cache" },
67 {}
68 };
69
70 U_BOOT_DRIVER(pl310_cache) = {
71 .name = "pl310_cache",
72 .id = UCLASS_CACHE,
73 .of_match = l2x0_ids,
74 .probe = l2x0_probe,
75 .flags = DM_FLAG_PRE_RELOC,
76 };
77