1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Author: Anup Patel <anup.patel@wdc.com>
6 */
7
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <div64.h>
11 #include <dm.h>
12
13 struct clk_fixed_factor {
14 struct clk parent;
15 unsigned int div;
16 unsigned int mult;
17 };
18
19 #define to_clk_fixed_factor(dev) \
20 ((struct clk_fixed_factor *)dev_get_platdata(dev))
21
clk_fixed_factor_get_rate(struct clk * clk)22 static ulong clk_fixed_factor_get_rate(struct clk *clk)
23 {
24 uint64_t rate;
25 struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
26
27 rate = clk_get_rate(&ff->parent);
28 if (IS_ERR_VALUE(rate))
29 return rate;
30
31 do_div(rate, ff->div);
32
33 return rate * ff->mult;
34 }
35
36 const struct clk_ops clk_fixed_factor_ops = {
37 .get_rate = clk_fixed_factor_get_rate,
38 };
39
clk_fixed_factor_ofdata_to_platdata(struct udevice * dev)40 static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
41 {
42 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
43 int err;
44 struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
45
46 err = clk_get_by_index(dev, 0, &ff->parent);
47 if (err)
48 return err;
49
50 ff->div = dev_read_u32_default(dev, "clock-div", 1);
51 ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
52 #endif
53
54 return 0;
55 }
56
57 static const struct udevice_id clk_fixed_factor_match[] = {
58 {
59 .compatible = "fixed-factor-clock",
60 },
61 { /* sentinel */ }
62 };
63
64 U_BOOT_DRIVER(clk_fixed_factor) = {
65 .name = "fixed_factor_clock",
66 .id = UCLASS_CLK,
67 .of_match = clk_fixed_factor_match,
68 .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
69 .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
70 .ops = &clk_fixed_factor_ops,
71 };
72