1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2018
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
7 #include <common.h>
8 #include <bitfield.h>
9 #include <clk.h>
10 #include <cpu.h>
11 #include <dm.h>
12 #include <vsprintf.h>
13
14 #include "mpc83xx_cpu.h"
15
16 /**
17 * struct mpc83xx_cpu_priv - Private data for MPC83xx CPUs
18 * @e300_type: The e300 core type of the MPC83xx CPU
19 * @family: The MPC83xx family the CPU belongs to
20 * @type: The MPC83xx type of the CPU
21 * @is_e_processor: Flag indicating whether the CPU is a E processor or not
22 * @is_a_variant: Flag indicating whtther the CPU is a A variant or not
23 * @revid: The revision ID of the CPU
24 * @revid.major: The major part of the CPU's revision ID
25 * @revid.minor: The minor part of the CPU's revision ID
26 */
27 struct mpc83xx_cpu_priv {
28 enum e300_type e300_type;
29 enum mpc83xx_cpu_family family;
30 enum mpc83xx_cpu_type type;
31 bool is_e_processor;
32 bool is_a_variant;
33 struct {
34 uint major;
35 uint minor;
36 } revid;
37 };
38
checkcpu(void)39 int checkcpu(void)
40 {
41 /* Activate all CPUs from board_f.c */
42 return cpu_probe_all();
43 }
44
45 /**
46 * get_spridr() - Read SPRIDR (System Part and Revision ID Register) of CPU
47 *
48 * Return: The SPRIDR value
49 */
get_spridr(void)50 static inline u32 get_spridr(void)
51 {
52 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
53
54 return in_be32(&immr->sysconf.spridr);
55 }
56
57 /**
58 * determine_type() - Determine CPU family of MPC83xx device
59 * @dev: CPU device from which to read CPU family from
60 */
determine_family(struct udevice * dev)61 static inline void determine_family(struct udevice *dev)
62 {
63 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
64 /* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */
65 const u32 PARTID_FAMILY_MASK = 0xFFF00000;
66
67 switch (bitfield_extract_by_mask(get_spridr(), PARTID_FAMILY_MASK)) {
68 case 0x810:
69 case 0x811:
70 priv->family = FAMILY_830X;
71 break;
72 case 0x80B:
73 priv->family = FAMILY_831X;
74 break;
75 case 0x806:
76 priv->family = FAMILY_832X;
77 break;
78 case 0x803:
79 priv->family = FAMILY_834X;
80 break;
81 case 0x804:
82 priv->family = FAMILY_836X;
83 break;
84 case 0x80C:
85 priv->family = FAMILY_837X;
86 break;
87 default:
88 priv->family = FAMILY_UNKNOWN;
89 }
90 }
91
92 /**
93 * determine_type() - Determine CPU type of MPC83xx device
94 * @dev: CPU device from which to read CPU type from
95 */
determine_type(struct udevice * dev)96 static inline void determine_type(struct udevice *dev)
97 {
98 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
99 /* Upper 16 bits of PVR (Processor Version Register) */
100 const u32 PCR_UPPER_MASK = 0xFFFF0000;
101 u32 val;
102
103 val = bitfield_extract_by_mask(get_spridr(), PCR_UPPER_MASK);
104
105 /* Mask out E-variant bit */
106 switch (val & 0xFFFE) {
107 case 0x8100:
108 priv->type = TYPE_8308;
109 break;
110 case 0x8110:
111 priv->type = TYPE_8309;
112 break;
113 case 0x80B2:
114 priv->type = TYPE_8311;
115 break;
116 case 0x80B0:
117 priv->type = TYPE_8313;
118 break;
119 case 0x80B6:
120 priv->type = TYPE_8314;
121 break;
122 case 0x80B4:
123 priv->type = TYPE_8315;
124 break;
125 case 0x8066:
126 priv->type = TYPE_8321;
127 break;
128 case 0x8062:
129 priv->type = TYPE_8323;
130 break;
131 case 0x8036:
132 priv->type = TYPE_8343;
133 break;
134 case 0x8032:
135 priv->type = TYPE_8347_TBGA;
136 break;
137 case 0x8034:
138 priv->type = TYPE_8347_PBGA;
139 break;
140 case 0x8030:
141 priv->type = TYPE_8349;
142 break;
143 case 0x804A:
144 priv->type = TYPE_8358_TBGA;
145 break;
146 case 0x804E:
147 priv->type = TYPE_8358_PBGA;
148 break;
149 case 0x8048:
150 priv->type = TYPE_8360;
151 break;
152 case 0x80C6:
153 priv->type = TYPE_8377;
154 break;
155 case 0x80C4:
156 priv->type = TYPE_8378;
157 break;
158 case 0x80C2:
159 priv->type = TYPE_8379;
160 break;
161 default:
162 priv->type = TYPE_UNKNOWN;
163 }
164 }
165
166 /**
167 * determine_e300_type() - Determine e300 core type of MPC83xx device
168 * @dev: CPU device from which to read e300 core type from
169 */
determine_e300_type(struct udevice * dev)170 static inline void determine_e300_type(struct udevice *dev)
171 {
172 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
173 /* Upper 16 bits of PVR (Processor Version Register) */
174 const u32 PCR_UPPER_MASK = 0xFFFF0000;
175 u32 pvr = get_pvr();
176
177 switch ((pvr & PCR_UPPER_MASK) >> 16) {
178 case 0x8083:
179 priv->e300_type = E300C1;
180 break;
181 case 0x8084:
182 priv->e300_type = E300C2;
183 break;
184 case 0x8085:
185 priv->e300_type = E300C3;
186 break;
187 case 0x8086:
188 priv->e300_type = E300C4;
189 break;
190 default:
191 priv->e300_type = E300_UNKNOWN;
192 }
193 }
194
195 /**
196 * determine_revid() - Determine revision ID of CPU device
197 * @dev: CPU device from which to read revision ID
198 */
determine_revid(struct udevice * dev)199 static inline void determine_revid(struct udevice *dev)
200 {
201 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
202 u32 REVID_MAJOR_MASK;
203 u32 REVID_MINOR_MASK;
204 u32 spridr = get_spridr();
205
206 if (priv->family == FAMILY_834X) {
207 REVID_MAJOR_MASK = 0x0000FF00;
208 REVID_MINOR_MASK = 0x000000FF;
209 } else {
210 REVID_MAJOR_MASK = 0x000000F0;
211 REVID_MINOR_MASK = 0x0000000F;
212 }
213
214 priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
215 priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
216 }
217
218 /**
219 * determine_cpu_data() - Determine CPU information from hardware
220 * @dev: CPU device from which to read information
221 */
determine_cpu_data(struct udevice * dev)222 static void determine_cpu_data(struct udevice *dev)
223 {
224 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
225 const u32 E_FLAG_MASK = 0x00010000;
226 u32 spridr = get_spridr();
227
228 determine_family(dev);
229 determine_type(dev);
230 determine_e300_type(dev);
231 determine_revid(dev);
232
233 if ((priv->family == FAMILY_834X ||
234 priv->family == FAMILY_836X) && priv->revid.major >= 2)
235 priv->is_a_variant = true;
236
237 priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
238 }
239
mpc83xx_cpu_get_desc(struct udevice * dev,char * buf,int size)240 static int mpc83xx_cpu_get_desc(struct udevice *dev, char *buf, int size)
241 {
242 struct mpc83xx_cpu_priv *priv = dev_get_priv(dev);
243 struct clk core_clk;
244 struct clk csb_clk;
245 char core_freq[32];
246 char csb_freq[32];
247 int ret;
248
249 ret = clk_get_by_index(dev, 0, &core_clk);
250 if (ret) {
251 debug("%s: Failed to get core clock (err = %d)\n",
252 dev->name, ret);
253 return ret;
254 }
255
256 ret = clk_get_by_index(dev, 1, &csb_clk);
257 if (ret) {
258 debug("%s: Failed to get CSB clock (err = %d)\n",
259 dev->name, ret);
260 return ret;
261 }
262
263 determine_cpu_data(dev);
264
265 snprintf(buf, size,
266 "%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz",
267 e300_names[priv->e300_type],
268 cpu_type_names[priv->type],
269 priv->is_e_processor ? "E" : "",
270 priv->is_a_variant ? "A" : "",
271 priv->revid.major,
272 priv->revid.minor,
273 strmhz(core_freq, clk_get_rate(&core_clk)),
274 strmhz(csb_freq, clk_get_rate(&csb_clk)));
275
276 return 0;
277 }
278
mpc83xx_cpu_get_info(struct udevice * dev,struct cpu_info * info)279 static int mpc83xx_cpu_get_info(struct udevice *dev, struct cpu_info *info)
280 {
281 struct clk clock;
282 int ret;
283 ulong freq;
284
285 ret = clk_get_by_index(dev, 0, &clock);
286 if (ret) {
287 debug("%s: Failed to get core clock (err = %d)\n",
288 dev->name, ret);
289 return ret;
290 }
291
292 freq = clk_get_rate(&clock);
293 if (!freq) {
294 debug("%s: Core clock speed is zero\n", dev->name);
295 return -EINVAL;
296 }
297
298 info->cpu_freq = freq;
299 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
300
301 return 0;
302 }
303
mpc83xx_cpu_get_count(struct udevice * dev)304 static int mpc83xx_cpu_get_count(struct udevice *dev)
305 {
306 /* We have one e300cX core */
307 return 1;
308 }
309
mpc83xx_cpu_get_vendor(struct udevice * dev,char * buf,int size)310 static int mpc83xx_cpu_get_vendor(struct udevice *dev, char *buf, int size)
311 {
312 snprintf(buf, size, "NXP");
313
314 return 0;
315 }
316
317 static const struct cpu_ops mpc83xx_cpu_ops = {
318 .get_desc = mpc83xx_cpu_get_desc,
319 .get_info = mpc83xx_cpu_get_info,
320 .get_count = mpc83xx_cpu_get_count,
321 .get_vendor = mpc83xx_cpu_get_vendor,
322 };
323
mpc83xx_cpu_probe(struct udevice * dev)324 static int mpc83xx_cpu_probe(struct udevice *dev)
325 {
326 return 0;
327 }
328
329 static const struct udevice_id mpc83xx_cpu_ids[] = {
330 { .compatible = "fsl,mpc83xx", },
331 { .compatible = "fsl,mpc8308", },
332 { .compatible = "fsl,mpc8309", },
333 { .compatible = "fsl,mpc8313", },
334 { .compatible = "fsl,mpc8315", },
335 { .compatible = "fsl,mpc832x", },
336 { .compatible = "fsl,mpc8349", },
337 { .compatible = "fsl,mpc8360", },
338 { .compatible = "fsl,mpc8379", },
339 { /* sentinel */ }
340 };
341
342 U_BOOT_DRIVER(mpc83xx_cpu) = {
343 .name = "mpc83xx_cpu",
344 .id = UCLASS_CPU,
345 .of_match = mpc83xx_cpu_ids,
346 .probe = mpc83xx_cpu_probe,
347 .priv_auto_alloc_size = sizeof(struct mpc83xx_cpu_priv),
348 .ops = &mpc83xx_cpu_ops,
349 .flags = DM_FLAG_PRE_RELOC,
350 };
351