1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #ifndef _SDRAM_S10_H_ 8 #define _SDRAM_S10_H_ 9 10 #define DDR_TWR 15 11 #define DDR_READ_LATENCY_DELAY 40 12 #define DDR_ACTIVATE_FAWBANK 0x1 13 14 /* ECC HMC registers */ 15 #define DDRIOCTRL 0x8 16 #define DDRCALSTAT 0xc 17 #define DRAMADDRWIDTH 0xe0 18 #define ECCCTRL1 0x100 19 #define ECCCTRL2 0x104 20 #define ERRINTEN 0x110 21 #define ERRINTENS 0x114 22 #define INTMODE 0x11c 23 #define INTSTAT 0x120 24 #define AUTOWB_CORRADDR 0x138 25 #define ECC_REG2WRECCDATABUS 0x144 26 #define ECC_DIAGON 0x150 27 #define ECC_DECSTAT 0x154 28 #define HPSINTFCSEL 0x210 29 #define RSTHANDSHAKECTRL 0x214 30 #define RSTHANDSHAKESTAT 0x218 31 32 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 33 #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) 34 #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) 35 #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) 36 #define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) 37 #define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) 38 #define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) 39 #define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) 40 #define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) 41 #define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) 42 #define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) 43 #define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) 44 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) 45 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) 46 #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) 47 #define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff 48 #define DDR_HMC_CORE2SEQ_INT_REQ 0xF 49 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) 50 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f 51 52 #define DDR_HMC_ERRINTEN_INTMASK \ 53 (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ 54 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) 55 56 /* NOC DDR scheduler */ 57 #define DDR_SCH_ID_COREID 0 58 #define DDR_SCH_ID_REVID 0x4 59 #define DDR_SCH_DDRCONF 0x8 60 #define DDR_SCH_DDRTIMING 0xc 61 #define DDR_SCH_DDRMODE 0x10 62 #define DDR_SCH_READ_LATENCY 0x14 63 #define DDR_SCH_ACTIVATE 0x38 64 #define DDR_SCH_DEVTODEV 0x3c 65 #define DDR_SCH_DDR4TIMING 0x40 66 67 #define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 68 #define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 69 #define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 70 #define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 71 #define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 72 #define DDR_SCH_DDRTIMING_WRTORD_OFF 26 73 #define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 74 #define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 75 #define DDR_SCH_ACTIVATE_RRD_OFF 0 76 #define DDR_SCH_ACTIVATE_FAW_OFF 4 77 #define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 78 #define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 79 #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 80 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4 81 82 /* HMC MMR IO48 registers */ 83 #define CTRLCFG0 0x28 84 #define CTRLCFG1 0x2c 85 #define DRAMTIMING0 0x50 86 #define CALTIMING0 0x7c 87 #define CALTIMING1 0x80 88 #define CALTIMING2 0x84 89 #define CALTIMING3 0x88 90 #define CALTIMING4 0x8c 91 #define CALTIMING9 0xa0 92 #define DRAMADDRW 0xa8 93 #define DRAMSTS 0xec 94 #define NIOSRESERVED0 0x110 95 #define NIOSRESERVED1 0x114 96 #define NIOSRESERVED2 0x118 97 98 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ 99 (((x) >> 0) & 0x1F) 100 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ 101 (((x) >> 5) & 0x1F) 102 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ 103 (((x) >> 10) & 0xF) 104 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ 105 (((x) >> 14) & 0x3) 106 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ 107 (((x) >> 16) & 0x7) 108 109 #define CTRLCFG0_CFG_MEMTYPE(x) \ 110 (((x) >> 0) & 0xF) 111 #define CTRLCFG0_CFG_DIMM_TYPE(x) \ 112 (((x) >> 4) & 0x7) 113 #define CTRLCFG0_CFG_AC_POS(x) \ 114 (((x) >> 7) & 0x3) 115 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ 116 (((x) >> 9) & 0x1F) 117 118 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ 119 (((x) >> 0) & 0x1F) 120 #define CTRLCFG1_CFG_ADDR_ORDER(x) \ 121 (((x) >> 5) & 0x3) 122 #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ 123 (((x) >> 7) & 0x1) 124 125 #define DRAMTIMING0_CFG_TCL(x) \ 126 (((x) >> 0) & 0x7F) 127 128 #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ 129 (((x) >> 0) & 0x3F) 130 #define CALTIMING0_CFG_ACT_TO_PCH(x) \ 131 (((x) >> 6) & 0x3F) 132 #define CALTIMING0_CFG_ACT_TO_ACT(x) \ 133 (((x) >> 12) & 0x3F) 134 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ 135 (((x) >> 18) & 0x3F) 136 137 #define CALTIMING1_CFG_RD_TO_RD(x) \ 138 (((x) >> 0) & 0x3F) 139 #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ 140 (((x) >> 6) & 0x3F) 141 #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ 142 (((x) >> 12) & 0x3F) 143 #define CALTIMING1_CFG_RD_TO_WR(x) \ 144 (((x) >> 18) & 0x3F) 145 #define CALTIMING1_CFG_RD_TO_WR_DC(x) \ 146 (((x) >> 24) & 0x3F) 147 148 #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ 149 (((x) >> 0) & 0x3F) 150 #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ 151 (((x) >> 6) & 0x3F) 152 #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ 153 (((x) >> 12) & 0x3F) 154 #define CALTIMING2_CFG_WR_TO_WR(x) \ 155 (((x) >> 18) & 0x3F) 156 #define CALTIMING2_CFG_WR_TO_WR_DC(x) \ 157 (((x) >> 24) & 0x3F) 158 159 #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ 160 (((x) >> 0) & 0x3F) 161 #define CALTIMING3_CFG_WR_TO_RD(x) \ 162 (((x) >> 6) & 0x3F) 163 #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ 164 (((x) >> 12) & 0x3F) 165 #define CALTIMING3_CFG_WR_TO_RD_DB(x) \ 166 (((x) >> 18) & 0x3F) 167 #define CALTIMING3_CFG_WR_TO_PCH(x) \ 168 (((x) >> 24) & 0x3F) 169 170 #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ 171 (((x) >> 0) & 0x3F) 172 #define CALTIMING4_CFG_PCH_TO_VALID(x) \ 173 (((x) >> 6) & 0x3F) 174 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ 175 (((x) >> 12) & 0x3F) 176 #define CALTIMING4_CFG_ARF_TO_VALID(x) \ 177 (((x) >> 18) & 0xFF) 178 #define CALTIMING4_CFG_PDN_TO_VALID(x) \ 179 (((x) >> 26) & 0x3F) 180 181 #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ 182 (((x) >> 0) & 0xFF) 183 184 /* Firewall DDR scheduler MPFE */ 185 #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 186 #define FW_HMC_ADAPTOR_MPU_MASK BIT(0) 187 188 #endif /* _SDRAM_S10_H_ */ 189