1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <spl.h>
8 #include <asm/io.h>
9 #include <errno.h>
10 #include <asm/io.h>
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/ddr.h>
13 #include <asm/arch/lpddr4_define.h>
14 #include <asm/sections.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define IMEM_LEN 32768 /* byte */
19 #define DMEM_LEN 16384 /* byte */
20 #define IMEM_2D_OFFSET 49152
21
22 #define IMEM_OFFSET_ADDR 0x00050000
23 #define DMEM_OFFSET_ADDR 0x00054000
24 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
25
26 /* We need PHY iMEM PHY is 32KB padded */
ddr_load_train_firmware(enum fw_type type)27 void ddr_load_train_firmware(enum fw_type type)
28 {
29 u32 tmp32, i;
30 u32 error = 0;
31 unsigned long pr_to32, pr_from32;
32 unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
33 unsigned long imem_start = (unsigned long)&_end + fw_offset;
34 unsigned long dmem_start;
35
36 #ifdef CONFIG_SPL_OF_CONTROL
37 if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
38 imem_start = roundup((unsigned long)&_end +
39 fdt_totalsize(gd->fdt_blob), 4) +
40 fw_offset;
41 }
42 #endif
43
44 dmem_start = imem_start + IMEM_LEN;
45
46 pr_from32 = imem_start;
47 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
48 for (i = 0x0; i < IMEM_LEN; ) {
49 tmp32 = readl(pr_from32);
50 writew(tmp32 & 0x0000ffff, pr_to32);
51 pr_to32 += 4;
52 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
53 pr_to32 += 4;
54 pr_from32 += 4;
55 i += 4;
56 }
57
58 pr_from32 = dmem_start;
59 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
60 for (i = 0x0; i < DMEM_LEN; ) {
61 tmp32 = readl(pr_from32);
62 writew(tmp32 & 0x0000ffff, pr_to32);
63 pr_to32 += 4;
64 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
65 pr_to32 += 4;
66 pr_from32 += 4;
67 i += 4;
68 }
69
70 debug("check ddr_pmu_train_imem code\n");
71 pr_from32 = imem_start;
72 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
73 for (i = 0x0; i < IMEM_LEN; ) {
74 tmp32 = (readw(pr_to32) & 0x0000ffff);
75 pr_to32 += 4;
76 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
77
78 if (tmp32 != readl(pr_from32)) {
79 debug("%lx %lx\n", pr_from32, pr_to32);
80 error++;
81 }
82 pr_from32 += 4;
83 pr_to32 += 4;
84 i += 4;
85 }
86 if (error)
87 printf("check ddr_pmu_train_imem code fail=%d\n", error);
88 else
89 debug("check ddr_pmu_train_imem code pass\n");
90
91 debug("check ddr4_pmu_train_dmem code\n");
92 pr_from32 = dmem_start;
93 pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
94 for (i = 0x0; i < DMEM_LEN;) {
95 tmp32 = (readw(pr_to32) & 0x0000ffff);
96 pr_to32 += 4;
97 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
98 if (tmp32 != readl(pr_from32)) {
99 debug("%lx %lx\n", pr_from32, pr_to32);
100 error++;
101 }
102 pr_from32 += 4;
103 pr_to32 += 4;
104 i += 4;
105 }
106
107 if (error)
108 printf("check ddr_pmu_train_dmem code fail=%d", error);
109 else
110 debug("check ddr_pmu_train_dmem code pass\n");
111 }
112
ddrphy_trained_csr_save(struct dram_cfg_param * ddrphy_csr,unsigned int num)113 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
114 unsigned int num)
115 {
116 int i = 0;
117
118 /* enable the ddrphy apb */
119 dwc_ddrphy_apb_wr(0xd0000, 0x0);
120 dwc_ddrphy_apb_wr(0xc0080, 0x3);
121 for (i = 0; i < num; i++) {
122 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
123 ddrphy_csr++;
124 }
125 /* disable the ddrphy apb */
126 dwc_ddrphy_apb_wr(0xc0080, 0x2);
127 dwc_ddrphy_apb_wr(0xd0000, 0x1);
128 }
129
dram_config_save(struct dram_timing_info * timing_info,unsigned long saved_timing_base)130 void dram_config_save(struct dram_timing_info *timing_info,
131 unsigned long saved_timing_base)
132 {
133 int i = 0;
134 struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
135 struct dram_cfg_param *cfg;
136
137 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
138 saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
139 saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
140 saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
141
142 /* save the fsp table */
143 for (i = 0; i < 4; i++)
144 saved_timing->fsp_table[i] = timing_info->fsp_table[i];
145
146 cfg = (struct dram_cfg_param *)(saved_timing_base +
147 sizeof(*timing_info));
148
149 /* save ddrc config */
150 saved_timing->ddrc_cfg = cfg;
151 for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
152 cfg->reg = timing_info->ddrc_cfg[i].reg;
153 cfg->val = timing_info->ddrc_cfg[i].val;
154 cfg++;
155 }
156
157 /* save ddrphy config */
158 saved_timing->ddrphy_cfg = cfg;
159 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
160 cfg->reg = timing_info->ddrphy_cfg[i].reg;
161 cfg->val = timing_info->ddrphy_cfg[i].val;
162 cfg++;
163 }
164
165 /* save the ddrphy csr */
166 saved_timing->ddrphy_trained_csr = cfg;
167 for (i = 0; i < ddrphy_trained_csr_num; i++) {
168 cfg->reg = ddrphy_trained_csr[i].reg;
169 cfg->val = ddrphy_trained_csr[i].val;
170 cfg++;
171 }
172
173 /* save the ddrphy pie */
174 saved_timing->ddrphy_pie = cfg;
175 for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
176 cfg->reg = timing_info->ddrphy_pie[i].reg;
177 cfg->val = timing_info->ddrphy_pie[i].val;
178 cfg++;
179 }
180 }
181