1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <cpu_func.h>
16 #include <errno.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <part.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/io.h>
24 #include <dm.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 struct fsl_esdhc {
29 uint dsaddr; /* SDMA system address register */
30 uint blkattr; /* Block attributes register */
31 uint cmdarg; /* Command argument register */
32 uint xfertyp; /* Transfer type register */
33 uint cmdrsp0; /* Command response 0 register */
34 uint cmdrsp1; /* Command response 1 register */
35 uint cmdrsp2; /* Command response 2 register */
36 uint cmdrsp3; /* Command response 3 register */
37 uint datport; /* Buffer data port register */
38 uint prsstat; /* Present state register */
39 uint proctl; /* Protocol control register */
40 uint sysctl; /* System Control Register */
41 uint irqstat; /* Interrupt status register */
42 uint irqstaten; /* Interrupt status enable register */
43 uint irqsigen; /* Interrupt signal enable register */
44 uint autoc12err; /* Auto CMD error status register */
45 uint hostcapblt; /* Host controller capabilities register */
46 uint wml; /* Watermark level register */
47 char reserved1[8]; /* reserved */
48 uint fevt; /* Force event register */
49 uint admaes; /* ADMA error status register */
50 uint adsaddr; /* ADMA system address register */
51 char reserved2[160];
52 uint hostver; /* Host controller version register */
53 char reserved3[4]; /* reserved */
54 uint dmaerraddr; /* DMA error address register */
55 char reserved4[4]; /* reserved */
56 uint dmaerrattr; /* DMA error attribute register */
57 char reserved5[4]; /* reserved */
58 uint hostcapblt2; /* Host controller capabilities register 2 */
59 char reserved6[756]; /* reserved */
60 uint esdhcctl; /* eSDHC control register */
61 };
62
63 struct fsl_esdhc_plat {
64 struct mmc_config cfg;
65 struct mmc mmc;
66 };
67
68 /**
69 * struct fsl_esdhc_priv
70 *
71 * @esdhc_regs: registers of the sdhc controller
72 * @sdhc_clk: Current clk of the sdhc controller
73 * @bus_width: bus width, 1bit, 4bit or 8bit
74 * @cfg: mmc config
75 * @mmc: mmc
76 * Following is used when Driver Model is enabled for MMC
77 * @dev: pointer for the device
78 * @cd_gpio: gpio for card detection
79 * @wp_gpio: gpio for write protection
80 */
81 struct fsl_esdhc_priv {
82 struct fsl_esdhc *esdhc_regs;
83 unsigned int sdhc_clk;
84 unsigned int clock;
85 #if !CONFIG_IS_ENABLED(DM_MMC)
86 struct mmc *mmc;
87 #endif
88 struct udevice *dev;
89 };
90
91 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)92 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
93 {
94 uint xfertyp = 0;
95
96 if (data) {
97 xfertyp |= XFERTYP_DPSEL;
98 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
99 xfertyp |= XFERTYP_DMAEN;
100 #endif
101 if (data->blocks > 1) {
102 xfertyp |= XFERTYP_MSBSEL;
103 xfertyp |= XFERTYP_BCEN;
104 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
105 xfertyp |= XFERTYP_AC12EN;
106 #endif
107 }
108
109 if (data->flags & MMC_DATA_READ)
110 xfertyp |= XFERTYP_DTDSEL;
111 }
112
113 if (cmd->resp_type & MMC_RSP_CRC)
114 xfertyp |= XFERTYP_CCCEN;
115 if (cmd->resp_type & MMC_RSP_OPCODE)
116 xfertyp |= XFERTYP_CICEN;
117 if (cmd->resp_type & MMC_RSP_136)
118 xfertyp |= XFERTYP_RSPTYP_136;
119 else if (cmd->resp_type & MMC_RSP_BUSY)
120 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
121 else if (cmd->resp_type & MMC_RSP_PRESENT)
122 xfertyp |= XFERTYP_RSPTYP_48;
123
124 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
125 xfertyp |= XFERTYP_CMDTYP_ABORT;
126
127 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
128 }
129
130 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
131 /*
132 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
133 */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)134 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
135 struct mmc_data *data)
136 {
137 struct fsl_esdhc *regs = priv->esdhc_regs;
138 uint blocks;
139 char *buffer;
140 uint databuf;
141 uint size;
142 uint irqstat;
143 ulong start;
144
145 if (data->flags & MMC_DATA_READ) {
146 blocks = data->blocks;
147 buffer = data->dest;
148 while (blocks) {
149 start = get_timer(0);
150 size = data->blocksize;
151 irqstat = esdhc_read32(®s->irqstat);
152 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
153 if (get_timer(start) > PIO_TIMEOUT) {
154 printf("\nData Read Failed in PIO Mode.");
155 return;
156 }
157 }
158 while (size && (!(irqstat & IRQSTAT_TC))) {
159 udelay(100); /* Wait before last byte transfer complete */
160 irqstat = esdhc_read32(®s->irqstat);
161 databuf = in_le32(®s->datport);
162 *((uint *)buffer) = databuf;
163 buffer += 4;
164 size -= 4;
165 }
166 blocks--;
167 }
168 } else {
169 blocks = data->blocks;
170 buffer = (char *)data->src;
171 while (blocks) {
172 start = get_timer(0);
173 size = data->blocksize;
174 irqstat = esdhc_read32(®s->irqstat);
175 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
176 if (get_timer(start) > PIO_TIMEOUT) {
177 printf("\nData Write Failed in PIO Mode.");
178 return;
179 }
180 }
181 while (size && (!(irqstat & IRQSTAT_TC))) {
182 udelay(100); /* Wait before last byte transfer complete */
183 databuf = *((uint *)buffer);
184 buffer += 4;
185 size -= 4;
186 irqstat = esdhc_read32(®s->irqstat);
187 out_le32(®s->datport, databuf);
188 }
189 blocks--;
190 }
191 }
192 }
193 #endif
194
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)195 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
196 struct mmc_data *data)
197 {
198 int timeout;
199 struct fsl_esdhc *regs = priv->esdhc_regs;
200 #if defined(CONFIG_FSL_LAYERSCAPE)
201 dma_addr_t addr;
202 #endif
203 uint wml_value;
204
205 wml_value = data->blocksize/4;
206
207 if (data->flags & MMC_DATA_READ) {
208 if (wml_value > WML_RD_WML_MAX)
209 wml_value = WML_RD_WML_MAX_VAL;
210
211 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
212 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
213 #if defined(CONFIG_FSL_LAYERSCAPE)
214 addr = virt_to_phys((void *)(data->dest));
215 if (upper_32_bits(addr))
216 printf("Error found for upper 32 bits\n");
217 else
218 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
219 #else
220 esdhc_write32(®s->dsaddr, (u32)data->dest);
221 #endif
222 #endif
223 } else {
224 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
225 flush_dcache_range((ulong)data->src,
226 (ulong)data->src+data->blocks
227 *data->blocksize);
228 #endif
229 if (wml_value > WML_WR_WML_MAX)
230 wml_value = WML_WR_WML_MAX_VAL;
231
232 if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
233 printf("Can not write to locked SD card.\n");
234 return -EINVAL;
235 }
236
237 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
238 wml_value << 16);
239 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
240 #if defined(CONFIG_FSL_LAYERSCAPE)
241 addr = virt_to_phys((void *)(data->src));
242 if (upper_32_bits(addr))
243 printf("Error found for upper 32 bits\n");
244 else
245 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
246 #else
247 esdhc_write32(®s->dsaddr, (u32)data->src);
248 #endif
249 #endif
250 }
251
252 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
253
254 /* Calculate the timeout period for data transactions */
255 /*
256 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
257 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
258 * So, Number of SD Clock cycles for 0.25sec should be minimum
259 * (SD Clock/sec * 0.25 sec) SD Clock cycles
260 * = (mmc->clock * 1/4) SD Clock cycles
261 * As 1) >= 2)
262 * => (2^(timeout+13)) >= mmc->clock * 1/4
263 * Taking log2 both the sides
264 * => timeout + 13 >= log2(mmc->clock/4)
265 * Rounding up to next power of 2
266 * => timeout + 13 = log2(mmc->clock/4) + 1
267 * => timeout + 13 = fls(mmc->clock/4)
268 *
269 * However, the MMC spec "It is strongly recommended for hosts to
270 * implement more than 500ms timeout value even if the card
271 * indicates the 250ms maximum busy length." Even the previous
272 * value of 300ms is known to be insufficient for some cards.
273 * So, we use
274 * => timeout + 13 = fls(mmc->clock/2)
275 */
276 timeout = fls(mmc->clock/2);
277 timeout -= 13;
278
279 if (timeout > 14)
280 timeout = 14;
281
282 if (timeout < 0)
283 timeout = 0;
284
285 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
286 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
287 timeout++;
288 #endif
289
290 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
291 timeout = 0xE;
292 #endif
293 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
294
295 return 0;
296 }
297
check_and_invalidate_dcache_range(struct mmc_cmd * cmd,struct mmc_data * data)298 static void check_and_invalidate_dcache_range
299 (struct mmc_cmd *cmd,
300 struct mmc_data *data) {
301 unsigned start = 0;
302 unsigned end = 0;
303 unsigned size = roundup(ARCH_DMA_MINALIGN,
304 data->blocks*data->blocksize);
305 #if defined(CONFIG_FSL_LAYERSCAPE)
306 dma_addr_t addr;
307
308 addr = virt_to_phys((void *)(data->dest));
309 if (upper_32_bits(addr))
310 printf("Error found for upper 32 bits\n");
311 else
312 start = lower_32_bits(addr);
313 #else
314 start = (unsigned)data->dest;
315 #endif
316 end = start + size;
317 invalidate_dcache_range(start, end);
318 }
319
320 /*
321 * Sends a command out on the bus. Takes the mmc pointer,
322 * a command pointer, and an optional data pointer.
323 */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)324 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
325 struct mmc_cmd *cmd, struct mmc_data *data)
326 {
327 int err = 0;
328 uint xfertyp;
329 uint irqstat;
330 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
331 struct fsl_esdhc *regs = priv->esdhc_regs;
332 unsigned long start;
333
334 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
335 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
336 return 0;
337 #endif
338
339 esdhc_write32(®s->irqstat, -1);
340
341 sync();
342
343 /* Wait for the bus to be idle */
344 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
345 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
346 ;
347
348 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
349 ;
350
351 /* Wait at least 8 SD clock cycles before the next command */
352 /*
353 * Note: This is way more than 8 cycles, but 1ms seems to
354 * resolve timing issues with some cards
355 */
356 udelay(1000);
357
358 /* Set up for a data transfer if we have one */
359 if (data) {
360 err = esdhc_setup_data(priv, mmc, data);
361 if(err)
362 return err;
363
364 if (data->flags & MMC_DATA_READ)
365 check_and_invalidate_dcache_range(cmd, data);
366 }
367
368 /* Figure out the transfer arguments */
369 xfertyp = esdhc_xfertyp(cmd, data);
370
371 /* Mask all irqs */
372 esdhc_write32(®s->irqsigen, 0);
373
374 /* Send the command */
375 esdhc_write32(®s->cmdarg, cmd->cmdarg);
376 esdhc_write32(®s->xfertyp, xfertyp);
377
378 /* Wait for the command to complete */
379 start = get_timer(0);
380 while (!(esdhc_read32(®s->irqstat) & flags)) {
381 if (get_timer(start) > 1000) {
382 err = -ETIMEDOUT;
383 goto out;
384 }
385 }
386
387 irqstat = esdhc_read32(®s->irqstat);
388
389 if (irqstat & CMD_ERR) {
390 err = -ECOMM;
391 goto out;
392 }
393
394 if (irqstat & IRQSTAT_CTOE) {
395 err = -ETIMEDOUT;
396 goto out;
397 }
398
399 /* Workaround for ESDHC errata ENGcm03648 */
400 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
401 int timeout = 6000;
402
403 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
404 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
405 PRSSTAT_DAT0)) {
406 udelay(100);
407 timeout--;
408 }
409
410 if (timeout <= 0) {
411 printf("Timeout waiting for DAT0 to go high!\n");
412 err = -ETIMEDOUT;
413 goto out;
414 }
415 }
416
417 /* Copy the response to the response buffer */
418 if (cmd->resp_type & MMC_RSP_136) {
419 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
420
421 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
422 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
423 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
424 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
425 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
426 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
427 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
428 cmd->response[3] = (cmdrsp0 << 8);
429 } else
430 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
431
432 /* Wait until all of the blocks are transferred */
433 if (data) {
434 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
435 esdhc_pio_read_write(priv, data);
436 #else
437 do {
438 irqstat = esdhc_read32(®s->irqstat);
439
440 if (irqstat & IRQSTAT_DTOE) {
441 err = -ETIMEDOUT;
442 goto out;
443 }
444
445 if (irqstat & DATA_ERR) {
446 err = -ECOMM;
447 goto out;
448 }
449 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
450
451 /*
452 * Need invalidate the dcache here again to avoid any
453 * cache-fill during the DMA operations such as the
454 * speculative pre-fetching etc.
455 */
456 if (data->flags & MMC_DATA_READ) {
457 check_and_invalidate_dcache_range(cmd, data);
458 }
459 #endif
460 }
461
462 out:
463 /* Reset CMD and DATA portions on error */
464 if (err) {
465 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
466 SYSCTL_RSTC);
467 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
468 ;
469
470 if (data) {
471 esdhc_write32(®s->sysctl,
472 esdhc_read32(®s->sysctl) |
473 SYSCTL_RSTD);
474 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
475 ;
476 }
477 }
478
479 esdhc_write32(®s->irqstat, -1);
480
481 return err;
482 }
483
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)484 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
485 {
486 struct fsl_esdhc *regs = priv->esdhc_regs;
487 int div = 1;
488 int pre_div = 2;
489 unsigned int sdhc_clk = priv->sdhc_clk;
490 u32 time_out;
491 u32 value;
492 uint clk;
493
494 if (clock < mmc->cfg->f_min)
495 clock = mmc->cfg->f_min;
496
497 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
498 pre_div *= 2;
499
500 while (sdhc_clk / (div * pre_div) > clock && div < 16)
501 div++;
502
503 pre_div >>= 1;
504 div -= 1;
505
506 clk = (pre_div << 8) | (div << 4);
507
508 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
509
510 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
511
512 time_out = 20;
513 value = PRSSTAT_SDSTB;
514 while (!(esdhc_read32(®s->prsstat) & value)) {
515 if (time_out == 0) {
516 printf("fsl_esdhc: Internal clock never stabilised.\n");
517 break;
518 }
519 time_out--;
520 mdelay(1);
521 }
522
523 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
524 }
525
526 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
esdhc_clock_control(struct fsl_esdhc_priv * priv,bool enable)527 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
528 {
529 struct fsl_esdhc *regs = priv->esdhc_regs;
530 u32 value;
531 u32 time_out;
532
533 value = esdhc_read32(®s->sysctl);
534
535 if (enable)
536 value |= SYSCTL_CKEN;
537 else
538 value &= ~SYSCTL_CKEN;
539
540 esdhc_write32(®s->sysctl, value);
541
542 time_out = 20;
543 value = PRSSTAT_SDSTB;
544 while (!(esdhc_read32(®s->prsstat) & value)) {
545 if (time_out == 0) {
546 printf("fsl_esdhc: Internal clock never stabilised.\n");
547 break;
548 }
549 time_out--;
550 mdelay(1);
551 }
552 }
553 #endif
554
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)555 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
556 {
557 struct fsl_esdhc *regs = priv->esdhc_regs;
558
559 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
560 /* Select to use peripheral clock */
561 esdhc_clock_control(priv, false);
562 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
563 esdhc_clock_control(priv, true);
564 #endif
565 /* Set the clock speed */
566 if (priv->clock != mmc->clock)
567 set_sysctl(priv, mmc, mmc->clock);
568
569 /* Set the bus width */
570 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
571
572 if (mmc->bus_width == 4)
573 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
574 else if (mmc->bus_width == 8)
575 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
576
577 return 0;
578 }
579
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)580 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
581 {
582 struct fsl_esdhc *regs = priv->esdhc_regs;
583 ulong start;
584
585 /* Reset the entire host controller */
586 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
587
588 /* Wait until the controller is available */
589 start = get_timer(0);
590 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
591 if (get_timer(start) > 1000)
592 return -ETIMEDOUT;
593 }
594
595 /* Enable cache snooping */
596 esdhc_write32(®s->esdhcctl, 0x00000040);
597
598 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
599
600 /* Set the initial clock speed */
601 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
602
603 /* Disable the BRR and BWR bits in IRQSTAT */
604 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
605
606 /* Put the PROCTL reg back to the default */
607 esdhc_write32(®s->proctl, PROCTL_INIT);
608
609 /* Set timout to the maximum value */
610 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
611
612 return 0;
613 }
614
esdhc_getcd_common(struct fsl_esdhc_priv * priv)615 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
616 {
617 struct fsl_esdhc *regs = priv->esdhc_regs;
618 int timeout = 1000;
619
620 #ifdef CONFIG_ESDHC_DETECT_QUIRK
621 if (CONFIG_ESDHC_DETECT_QUIRK)
622 return 1;
623 #endif
624 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
625 udelay(1000);
626
627 return timeout > 0;
628 }
629
fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv * priv,struct mmc_config * cfg)630 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
631 struct mmc_config *cfg)
632 {
633 struct fsl_esdhc *regs = priv->esdhc_regs;
634 u32 caps;
635
636 caps = esdhc_read32(®s->hostcapblt);
637 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
638 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
639 #endif
640 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
641 caps |= HOSTCAPBLT_VS33;
642 #endif
643 if (caps & HOSTCAPBLT_VS18)
644 cfg->voltages |= MMC_VDD_165_195;
645 if (caps & HOSTCAPBLT_VS30)
646 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
647 if (caps & HOSTCAPBLT_VS33)
648 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
649
650 cfg->name = "FSL_SDHC";
651
652 if (caps & HOSTCAPBLT_HSS)
653 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
654
655 cfg->f_min = 400000;
656 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
657 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
658 }
659
660 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
mmc_adapter_card_type_ident(void)661 void mmc_adapter_card_type_ident(void)
662 {
663 u8 card_id;
664 u8 value;
665
666 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
667 gd->arch.sdhc_adapter = card_id;
668
669 switch (card_id) {
670 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
671 value = QIXIS_READ(brdcfg[5]);
672 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
673 QIXIS_WRITE(brdcfg[5], value);
674 break;
675 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
676 value = QIXIS_READ(pwr_ctl[1]);
677 value |= QIXIS_EVDD_BY_SDHC_VS;
678 QIXIS_WRITE(pwr_ctl[1], value);
679 break;
680 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
681 value = QIXIS_READ(brdcfg[5]);
682 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
683 QIXIS_WRITE(brdcfg[5], value);
684 break;
685 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
686 break;
687 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
688 break;
689 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
690 break;
691 case QIXIS_ESDHC_NO_ADAPTER:
692 break;
693 default:
694 break;
695 }
696 }
697 #endif
698
699 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)700 __weak int esdhc_status_fixup(void *blob, const char *compat)
701 {
702 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
703 if (!hwconfig("esdhc")) {
704 do_fixup_by_compat(blob, compat, "status", "disabled",
705 sizeof("disabled"), 1);
706 return 1;
707 }
708 #endif
709 return 0;
710 }
711
fdt_fixup_esdhc(void * blob,bd_t * bd)712 void fdt_fixup_esdhc(void *blob, bd_t *bd)
713 {
714 const char *compat = "fsl,esdhc";
715
716 if (esdhc_status_fixup(blob, compat))
717 return;
718
719 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
720 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
721 gd->arch.sdhc_clk, 1);
722 #else
723 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
724 gd->arch.sdhc_clk, 1);
725 #endif
726 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
727 do_fixup_by_compat_u32(blob, compat, "adapter-type",
728 (u32)(gd->arch.sdhc_adapter), 1);
729 #endif
730 }
731 #endif
732
733 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)734 static int esdhc_getcd(struct mmc *mmc)
735 {
736 struct fsl_esdhc_priv *priv = mmc->priv;
737
738 return esdhc_getcd_common(priv);
739 }
740
esdhc_init(struct mmc * mmc)741 static int esdhc_init(struct mmc *mmc)
742 {
743 struct fsl_esdhc_priv *priv = mmc->priv;
744
745 return esdhc_init_common(priv, mmc);
746 }
747
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)748 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
749 struct mmc_data *data)
750 {
751 struct fsl_esdhc_priv *priv = mmc->priv;
752
753 return esdhc_send_cmd_common(priv, mmc, cmd, data);
754 }
755
esdhc_set_ios(struct mmc * mmc)756 static int esdhc_set_ios(struct mmc *mmc)
757 {
758 struct fsl_esdhc_priv *priv = mmc->priv;
759
760 return esdhc_set_ios_common(priv, mmc);
761 }
762
763 static const struct mmc_ops esdhc_ops = {
764 .getcd = esdhc_getcd,
765 .init = esdhc_init,
766 .send_cmd = esdhc_send_cmd,
767 .set_ios = esdhc_set_ios,
768 };
769
fsl_esdhc_initialize(bd_t * bis,struct fsl_esdhc_cfg * cfg)770 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
771 {
772 struct fsl_esdhc_plat *plat;
773 struct fsl_esdhc_priv *priv;
774 struct mmc_config *mmc_cfg;
775 struct mmc *mmc;
776
777 if (!cfg)
778 return -EINVAL;
779
780 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
781 if (!priv)
782 return -ENOMEM;
783 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
784 if (!plat) {
785 free(priv);
786 return -ENOMEM;
787 }
788
789 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
790 priv->sdhc_clk = cfg->sdhc_clk;
791
792 mmc_cfg = &plat->cfg;
793
794 if (cfg->max_bus_width == 8) {
795 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
796 MMC_MODE_8BIT;
797 } else if (cfg->max_bus_width == 4) {
798 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
799 } else if (cfg->max_bus_width == 1) {
800 mmc_cfg->host_caps |= MMC_MODE_1BIT;
801 } else {
802 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
803 MMC_MODE_8BIT;
804 printf("No max bus width provided. Assume 8-bit supported.\n");
805 }
806
807 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
808 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
809 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
810 #endif
811 mmc_cfg->ops = &esdhc_ops;
812
813 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
814
815 mmc = mmc_create(mmc_cfg, priv);
816 if (!mmc)
817 return -EIO;
818
819 priv->mmc = mmc;
820 return 0;
821 }
822
fsl_esdhc_mmc_init(bd_t * bis)823 int fsl_esdhc_mmc_init(bd_t *bis)
824 {
825 struct fsl_esdhc_cfg *cfg;
826
827 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
828 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
829 cfg->sdhc_clk = gd->arch.sdhc_clk;
830 return fsl_esdhc_initialize(bis, cfg);
831 }
832 #else /* DM_MMC */
fsl_esdhc_probe(struct udevice * dev)833 static int fsl_esdhc_probe(struct udevice *dev)
834 {
835 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
836 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
837 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
838 fdt_addr_t addr;
839 struct mmc *mmc;
840
841 addr = dev_read_addr(dev);
842 if (addr == FDT_ADDR_T_NONE)
843 return -EINVAL;
844 #ifdef CONFIG_PPC
845 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
846 #else
847 priv->esdhc_regs = (struct fsl_esdhc *)addr;
848 #endif
849 priv->dev = dev;
850
851 priv->sdhc_clk = gd->arch.sdhc_clk;
852 if (priv->sdhc_clk <= 0) {
853 dev_err(dev, "Unable to get clk for %s\n", dev->name);
854 return -EINVAL;
855 }
856
857 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
858
859 mmc_of_parse(dev, &plat->cfg);
860
861 mmc = &plat->mmc;
862 mmc->cfg = &plat->cfg;
863 mmc->dev = dev;
864
865 upriv->mmc = mmc;
866
867 return esdhc_init_common(priv, mmc);
868 }
869
fsl_esdhc_get_cd(struct udevice * dev)870 static int fsl_esdhc_get_cd(struct udevice *dev)
871 {
872 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
873 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
874
875 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
876 return 1;
877
878 return esdhc_getcd_common(priv);
879 }
880
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)881 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
882 struct mmc_data *data)
883 {
884 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
885 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
886
887 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
888 }
889
fsl_esdhc_set_ios(struct udevice * dev)890 static int fsl_esdhc_set_ios(struct udevice *dev)
891 {
892 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
893 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
894
895 return esdhc_set_ios_common(priv, &plat->mmc);
896 }
897
898 static const struct dm_mmc_ops fsl_esdhc_ops = {
899 .get_cd = fsl_esdhc_get_cd,
900 .send_cmd = fsl_esdhc_send_cmd,
901 .set_ios = fsl_esdhc_set_ios,
902 #ifdef MMC_SUPPORTS_TUNING
903 .execute_tuning = fsl_esdhc_execute_tuning,
904 #endif
905 };
906
907 static const struct udevice_id fsl_esdhc_ids[] = {
908 { .compatible = "fsl,esdhc", },
909 { /* sentinel */ }
910 };
911
fsl_esdhc_bind(struct udevice * dev)912 static int fsl_esdhc_bind(struct udevice *dev)
913 {
914 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
915
916 return mmc_bind(dev, &plat->mmc, &plat->cfg);
917 }
918
919 U_BOOT_DRIVER(fsl_esdhc) = {
920 .name = "fsl-esdhc-mmc",
921 .id = UCLASS_MMC,
922 .of_match = fsl_esdhc_ids,
923 .ops = &fsl_esdhc_ops,
924 .bind = fsl_esdhc_bind,
925 .probe = fsl_esdhc_probe,
926 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
927 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
928 };
929 #endif
930