1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX28 SSP MMC driver
4 *
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7 *
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
10 *
11 * Based on code from LTIB:
12 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
13 * Terry Lv
14 *
15 * Copyright 2007, Freescale Semiconductor, Inc
16 * Andy Fleming
17 *
18 * Based vaguely on the pxa mmc code:
19 * (C) Copyright 2003
20 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 */
22
23 #include <common.h>
24 #include <malloc.h>
25 #include <mmc.h>
26 #include <linux/errno.h>
27 #include <asm/io.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/mach-imx/dma.h>
32 #include <bouncebuf.h>
33
34 #define MXSMMC_MAX_TIMEOUT 10000
35 #define MXSMMC_SMALL_TRANSFER 512
36
37 #if !CONFIG_IS_ENABLED(DM_MMC)
38 struct mxsmmc_priv {
39 int id;
40 int (*mmc_is_wp)(int);
41 int (*mmc_cd)(int);
42 struct mmc_config cfg; /* mmc configuration */
43 struct mxs_dma_desc *desc;
44 uint32_t buswidth;
45 struct mxs_ssp_regs *regs;
46 };
47 #else /* CONFIG_IS_ENABLED(DM_MMC) */
48 #include <dm/device.h>
49 #include <dm/read.h>
50 #include <dt-structs.h>
51
52 #ifdef CONFIG_MX28
53 #define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
54 #else /* CONFIG_MX23 */
55 #define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
56 #endif
57
58 struct mxsmmc_platdata {
59 #if CONFIG_IS_ENABLED(OF_PLATDATA)
60 struct dtd_fsl_imx_mmc dtplat;
61 #endif
62 struct mmc_config cfg;
63 struct mmc mmc;
64 fdt_addr_t base;
65 int non_removable;
66 int buswidth;
67 int dma_id;
68 int clk_id;
69 };
70
71 struct mxsmmc_priv {
72 int clkid;
73 struct mxs_dma_desc *desc;
74 u32 buswidth;
75 struct mxs_ssp_regs *regs;
76 unsigned int dma_channel;
77 };
78 #endif
79
80 #if !CONFIG_IS_ENABLED(DM_MMC)
81 static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
82 struct mmc_data *data);
83
mxsmmc_cd(struct mxsmmc_priv * priv)84 static int mxsmmc_cd(struct mxsmmc_priv *priv)
85 {
86 struct mxs_ssp_regs *ssp_regs = priv->regs;
87
88 if (priv->mmc_cd)
89 return priv->mmc_cd(priv->id);
90
91 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
92 }
93
mxsmmc_set_ios(struct mmc * mmc)94 static int mxsmmc_set_ios(struct mmc *mmc)
95 {
96 struct mxsmmc_priv *priv = mmc->priv;
97 struct mxs_ssp_regs *ssp_regs = priv->regs;
98
99 /* Set the clock speed */
100 if (mmc->clock)
101 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
102
103 switch (mmc->bus_width) {
104 case 1:
105 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
106 break;
107 case 4:
108 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
109 break;
110 case 8:
111 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
112 break;
113 }
114
115 /* Set the bus width */
116 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
117 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
118
119 debug("MMC%d: Set %d bits bus width\n",
120 mmc->block_dev.devnum, mmc->bus_width);
121
122 return 0;
123 }
124
mxsmmc_init(struct mmc * mmc)125 static int mxsmmc_init(struct mmc *mmc)
126 {
127 struct mxsmmc_priv *priv = mmc->priv;
128 struct mxs_ssp_regs *ssp_regs = priv->regs;
129
130 /* Reset SSP */
131 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
132
133 /* Reconfigure the SSP block for MMC operation */
134 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
135 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
136 SSP_CTRL1_DMA_ENABLE |
137 SSP_CTRL1_POLARITY |
138 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
139 SSP_CTRL1_DATA_CRC_IRQ_EN |
140 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
141 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
142 SSP_CTRL1_RESP_ERR_IRQ_EN,
143 &ssp_regs->hw_ssp_ctrl1_set);
144
145 /* Set initial bit clock 400 KHz */
146 mxs_set_ssp_busclock(priv->id, 400);
147
148 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
149 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
150 udelay(200);
151 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
152
153 return 0;
154 }
155
156 static const struct mmc_ops mxsmmc_ops = {
157 .send_cmd = mxsmmc_send_cmd,
158 .set_ios = mxsmmc_set_ios,
159 .init = mxsmmc_init,
160 };
161
mxsmmc_initialize(bd_t * bis,int id,int (* wp)(int),int (* cd)(int))162 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
163 {
164 struct mmc *mmc = NULL;
165 struct mxsmmc_priv *priv = NULL;
166 int ret;
167 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
168
169 if (!mxs_ssp_bus_id_valid(id))
170 return -ENODEV;
171
172 priv = malloc(sizeof(struct mxsmmc_priv));
173 if (!priv)
174 return -ENOMEM;
175
176 priv->desc = mxs_dma_desc_alloc();
177 if (!priv->desc) {
178 free(priv);
179 return -ENOMEM;
180 }
181
182 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
183 if (ret)
184 return ret;
185
186 priv->mmc_is_wp = wp;
187 priv->mmc_cd = cd;
188 priv->id = id;
189 priv->regs = mxs_ssp_regs_by_bus(id);
190
191 priv->cfg.name = "MXS MMC";
192 priv->cfg.ops = &mxsmmc_ops;
193
194 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
195
196 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
197 MMC_MODE_HS_52MHz | MMC_MODE_HS;
198
199 /*
200 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
201 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
202 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
203 * CLOCK_RATE could be any integer from 0 to 255.
204 */
205 priv->cfg.f_min = 400000;
206 priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
207 * 1000 / 2;
208 priv->cfg.b_max = 0x20;
209
210 mmc = mmc_create(&priv->cfg, priv);
211 if (!mmc) {
212 mxs_dma_desc_free(priv->desc);
213 free(priv);
214 return -ENOMEM;
215 }
216 return 0;
217 }
218 #endif /* CONFIG_IS_ENABLED(DM_MMC) */
219
mxsmmc_send_cmd_pio(struct mxsmmc_priv * priv,struct mmc_data * data)220 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
221 {
222 struct mxs_ssp_regs *ssp_regs = priv->regs;
223 uint32_t *data_ptr;
224 int timeout = MXSMMC_MAX_TIMEOUT;
225 uint32_t reg;
226 uint32_t data_count = data->blocksize * data->blocks;
227
228 if (data->flags & MMC_DATA_READ) {
229 data_ptr = (uint32_t *)data->dest;
230 while (data_count && --timeout) {
231 reg = readl(&ssp_regs->hw_ssp_status);
232 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
233 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
234 data_count -= 4;
235 timeout = MXSMMC_MAX_TIMEOUT;
236 } else
237 udelay(1000);
238 }
239 } else {
240 data_ptr = (uint32_t *)data->src;
241 timeout *= 100;
242 while (data_count && --timeout) {
243 reg = readl(&ssp_regs->hw_ssp_status);
244 if (!(reg & SSP_STATUS_FIFO_FULL)) {
245 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
246 data_count -= 4;
247 timeout = MXSMMC_MAX_TIMEOUT;
248 } else
249 udelay(1000);
250 }
251 }
252
253 return timeout ? 0 : -ECOMM;
254 }
255
mxsmmc_send_cmd_dma(struct mxsmmc_priv * priv,struct mmc_data * data)256 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
257 {
258 uint32_t data_count = data->blocksize * data->blocks;
259 int dmach;
260 struct mxs_dma_desc *desc = priv->desc;
261 void *addr;
262 unsigned int flags;
263 struct bounce_buffer bbstate;
264
265 memset(desc, 0, sizeof(struct mxs_dma_desc));
266 desc->address = (dma_addr_t)desc;
267
268 if (data->flags & MMC_DATA_READ) {
269 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
270 addr = data->dest;
271 flags = GEN_BB_WRITE;
272 } else {
273 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
274 addr = (void *)data->src;
275 flags = GEN_BB_READ;
276 }
277
278 bounce_buffer_start(&bbstate, addr, data_count, flags);
279
280 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
281
282 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
283 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
284
285 #if !CONFIG_IS_ENABLED(DM_MMC)
286 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
287 #else
288 dmach = priv->dma_channel;
289 #endif
290 mxs_dma_desc_append(dmach, priv->desc);
291 if (mxs_dma_go(dmach)) {
292 bounce_buffer_stop(&bbstate);
293 return -ECOMM;
294 }
295
296 bounce_buffer_stop(&bbstate);
297
298 return 0;
299 }
300
301 #if !CONFIG_IS_ENABLED(DM_MMC)
302 /*
303 * Sends a command out on the bus. Takes the mmc pointer,
304 * a command pointer, and an optional data pointer.
305 */
306 static int
mxsmmc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)307 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
308 {
309 struct mxsmmc_priv *priv = mmc->priv;
310 struct mxs_ssp_regs *ssp_regs = priv->regs;
311 #else
312 static int
313 mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
314 {
315 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
316 struct mxsmmc_priv *priv = dev_get_priv(dev);
317 struct mxs_ssp_regs *ssp_regs = priv->regs;
318 struct mmc *mmc = &plat->mmc;
319 #endif
320 uint32_t reg;
321 int timeout;
322 uint32_t ctrl0;
323 int ret;
324 #if !CONFIG_IS_ENABLED(DM_MMC)
325 int devnum = mmc->block_dev.devnum;
326 #else
327 int devnum = mmc_get_blk_desc(mmc)->devnum;
328 #endif
329 debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
330
331 /* Check bus busy */
332 timeout = MXSMMC_MAX_TIMEOUT;
333 while (--timeout) {
334 udelay(1000);
335 reg = readl(&ssp_regs->hw_ssp_status);
336 if (!(reg &
337 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
338 SSP_STATUS_CMD_BUSY))) {
339 break;
340 }
341 }
342
343 if (!timeout) {
344 printf("MMC%d: Bus busy timeout!\n", devnum);
345 return -ETIMEDOUT;
346 }
347 #if !CONFIG_IS_ENABLED(DM_MMC)
348 /* See if card is present */
349 if (!mxsmmc_cd(priv)) {
350 printf("MMC%d: No card detected!\n", devnum);
351 return -ENOMEDIUM;
352 }
353 #endif
354 /* Start building CTRL0 contents */
355 ctrl0 = priv->buswidth;
356
357 /* Set up command */
358 if (!(cmd->resp_type & MMC_RSP_CRC))
359 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
360 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
361 ctrl0 |= SSP_CTRL0_GET_RESP;
362 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
363 ctrl0 |= SSP_CTRL0_LONG_RESP;
364
365 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
366 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
367 else
368 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
369
370 /* Command index */
371 reg = readl(&ssp_regs->hw_ssp_cmd0);
372 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
373 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
374 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
375 reg |= SSP_CMD0_APPEND_8CYC;
376 writel(reg, &ssp_regs->hw_ssp_cmd0);
377
378 /* Command argument */
379 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
380
381 /* Set up data */
382 if (data) {
383 /* READ or WRITE */
384 if (data->flags & MMC_DATA_READ) {
385 ctrl0 |= SSP_CTRL0_READ;
386 #if !CONFIG_IS_ENABLED(DM_MMC)
387 } else if (priv->mmc_is_wp &&
388 priv->mmc_is_wp(devnum)) {
389 printf("MMC%d: Can not write a locked card!\n", devnum);
390 return -EOPNOTSUPP;
391 #endif
392 }
393 ctrl0 |= SSP_CTRL0_DATA_XFER;
394
395 reg = data->blocksize * data->blocks;
396 #if defined(CONFIG_MX23)
397 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
398
399 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
400 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
401 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
402 ((ffs(data->blocksize) - 1) <<
403 SSP_CMD0_BLOCK_SIZE_OFFSET));
404 #elif defined(CONFIG_MX28)
405 writel(reg, &ssp_regs->hw_ssp_xfer_size);
406
407 reg = ((data->blocks - 1) <<
408 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
409 ((ffs(data->blocksize) - 1) <<
410 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
411 writel(reg, &ssp_regs->hw_ssp_block_size);
412 #endif
413 }
414
415 /* Kick off the command */
416 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
417 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
418
419 /* Wait for the command to complete */
420 timeout = MXSMMC_MAX_TIMEOUT;
421 while (--timeout) {
422 udelay(1000);
423 reg = readl(&ssp_regs->hw_ssp_status);
424 if (!(reg & SSP_STATUS_CMD_BUSY))
425 break;
426 }
427
428 if (!timeout) {
429 printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
430 return -ETIMEDOUT;
431 }
432
433 /* Check command timeout */
434 if (reg & SSP_STATUS_RESP_TIMEOUT) {
435 debug("MMC%d: Command %d timeout (status 0x%08x)\n",
436 devnum, cmd->cmdidx, reg);
437 return -ETIMEDOUT;
438 }
439
440 /* Check command errors */
441 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
442 printf("MMC%d: Command %d error (status 0x%08x)!\n",
443 devnum, cmd->cmdidx, reg);
444 return -ECOMM;
445 }
446
447 /* Copy response to response buffer */
448 if (cmd->resp_type & MMC_RSP_136) {
449 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
450 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
451 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
452 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
453 } else
454 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
455
456 /* Return if no data to process */
457 if (!data)
458 return 0;
459
460 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
461 ret = mxsmmc_send_cmd_pio(priv, data);
462 if (ret) {
463 printf("MMC%d: Data timeout with command %d "
464 "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
465 return ret;
466 }
467 } else {
468 ret = mxsmmc_send_cmd_dma(priv, data);
469 if (ret) {
470 printf("MMC%d: DMA transfer failed\n", devnum);
471 return ret;
472 }
473 }
474
475 /* Check data errors */
476 reg = readl(&ssp_regs->hw_ssp_status);
477 if (reg &
478 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
479 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
480 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
481 devnum, cmd->cmdidx, reg);
482 return -ECOMM;
483 }
484
485 return 0;
486 }
487
488 #if CONFIG_IS_ENABLED(DM_MMC)
489 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
490 #define MXS_SSP_IMX23_CLKID_SSP0 33
491 #define MXS_SSP_IMX28_CLKID_SSP0 46
492
493 static int mxsmmc_get_cd(struct udevice *dev)
494 {
495 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
496 struct mxsmmc_priv *priv = dev_get_priv(dev);
497 struct mxs_ssp_regs *ssp_regs = priv->regs;
498
499 if (plat->non_removable)
500 return 1;
501
502 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
503 }
504
505 static int mxsmmc_set_ios(struct udevice *dev)
506 {
507 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
508 struct mxsmmc_priv *priv = dev_get_priv(dev);
509 struct mxs_ssp_regs *ssp_regs = priv->regs;
510 struct mmc *mmc = &plat->mmc;
511
512 /* Set the clock speed */
513 if (mmc->clock)
514 mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
515
516 switch (mmc->bus_width) {
517 case 1:
518 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
519 break;
520 case 4:
521 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
522 break;
523 case 8:
524 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
525 break;
526 }
527
528 /* Set the bus width */
529 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
530 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
531
532 debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
533 mmc->bus_width);
534
535 return 0;
536 }
537
538 static int mxsmmc_init(struct udevice *dev)
539 {
540 struct mxsmmc_priv *priv = dev_get_priv(dev);
541 struct mxs_ssp_regs *ssp_regs = priv->regs;
542
543 /* Reset SSP */
544 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
545
546 /* Reconfigure the SSP block for MMC operation */
547 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
548 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
549 SSP_CTRL1_DMA_ENABLE |
550 SSP_CTRL1_POLARITY |
551 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
552 SSP_CTRL1_DATA_CRC_IRQ_EN |
553 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
554 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
555 SSP_CTRL1_RESP_ERR_IRQ_EN,
556 &ssp_regs->hw_ssp_ctrl1_set);
557
558 /* Set initial bit clock 400 KHz */
559 mxs_set_ssp_busclock(priv->clkid, 400);
560
561 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
562 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
563 udelay(200);
564 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
565
566 return 0;
567 }
568
569 static int mxsmmc_probe(struct udevice *dev)
570 {
571 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
572 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
573 struct mxsmmc_priv *priv = dev_get_priv(dev);
574 struct blk_desc *bdesc;
575 struct mmc *mmc;
576 int ret, clkid;
577
578 debug("%s: probe\n", __func__);
579
580 #if CONFIG_IS_ENABLED(OF_PLATDATA)
581 struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
582 struct phandle_1_arg *p1a = &dtplat->clocks[0];
583
584 priv->buswidth = dtplat->bus_width;
585 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
586 priv->dma_channel = dtplat->dmas[1];
587 clkid = p1a->arg[0];
588 plat->non_removable = dtplat->non_removable;
589
590 debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
591 priv->regs, priv->buswidth, clkid, plat->non_removable);
592 #else
593 priv->regs = (struct mxs_ssp_regs *)plat->base;
594 priv->dma_channel = plat->dma_id;
595 clkid = plat->clk_id;
596 #endif
597
598 #ifdef CONFIG_MX28
599 priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
600 #else /* CONFIG_MX23 */
601 priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
602 #endif
603 mmc = &plat->mmc;
604 mmc->cfg = &plat->cfg;
605 mmc->dev = dev;
606
607 priv->desc = mxs_dma_desc_alloc();
608 if (!priv->desc) {
609 printf("%s: Cannot allocate DMA descriptor\n", __func__);
610 return -ENOMEM;
611 }
612
613 ret = mxs_dma_init_channel(priv->dma_channel);
614 if (ret)
615 return ret;
616
617 plat->cfg.name = "MXS MMC";
618 plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
619
620 plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
621 MMC_MODE_HS_52MHz | MMC_MODE_HS;
622
623 /*
624 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
625 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
626 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
627 * CLOCK_RATE could be any integer from 0 to 255.
628 */
629 plat->cfg.f_min = 400000;
630 plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
631 plat->cfg.b_max = 0x20;
632
633 bdesc = mmc_get_blk_desc(mmc);
634 if (!bdesc) {
635 printf("%s: No block device descriptor!\n", __func__);
636 return -ENODEV;
637 }
638
639 if (plat->non_removable)
640 bdesc->removable = 0;
641
642 ret = mxsmmc_init(dev);
643 if (ret)
644 printf("%s: MMC%d init error %d\n", __func__,
645 bdesc->devnum, ret);
646
647 /* Set the initial clock speed */
648 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
649
650 upriv->mmc = mmc;
651
652 return 0;
653 };
654
655 #if CONFIG_IS_ENABLED(BLK)
656 static int mxsmmc_bind(struct udevice *dev)
657 {
658 struct mxsmmc_platdata *plat = dev_get_platdata(dev);
659
660 return mmc_bind(dev, &plat->mmc, &plat->cfg);
661 }
662 #endif
663
664 static const struct dm_mmc_ops mxsmmc_ops = {
665 .get_cd = mxsmmc_get_cd,
666 .send_cmd = mxsmmc_send_cmd,
667 .set_ios = mxsmmc_set_ios,
668 };
669
670 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
671 static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
672 {
673 struct mxsmmc_platdata *plat = bus->platdata;
674 u32 prop[2];
675 int ret;
676
677 plat->base = dev_read_addr(bus);
678 plat->buswidth =
679 dev_read_u32_default(bus, "bus-width", 1);
680 plat->non_removable = dev_read_bool(bus, "non-removable");
681
682 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
683 if (ret) {
684 printf("%s: Reading 'dmas' property failed!\n", __func__);
685 return ret;
686 }
687 plat->dma_id = prop[1];
688
689 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
690 if (ret) {
691 printf("%s: Reading 'clocks' property failed!\n", __func__);
692 return ret;
693 }
694 plat->clk_id = prop[1];
695
696 debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
697 __func__, (uint)plat->base, plat->buswidth,
698 plat->non_removable ? "non-removable" : NULL,
699 plat->dma_id, plat->clk_id);
700
701 return 0;
702 }
703
704 static const struct udevice_id mxsmmc_ids[] = {
705 { .compatible = "fsl,imx23-mmc", },
706 { .compatible = "fsl,imx28-mmc", },
707 { /* sentinel */ }
708 };
709 #endif
710
711 U_BOOT_DRIVER(mxsmmc) = {
712 #ifdef CONFIG_MX28
713 .name = "fsl_imx28_mmc",
714 #else /* CONFIG_MX23 */
715 .name = "fsl_imx23_mmc",
716 #endif
717 .id = UCLASS_MMC,
718 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
719 .of_match = mxsmmc_ids,
720 .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
721 #endif
722 .ops = &mxsmmc_ops,
723 #if CONFIG_IS_ENABLED(BLK)
724 .bind = mxsmmc_bind,
725 #endif
726 .probe = mxsmmc_probe,
727 .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
728 .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
729 };
730
731 #endif /* CONFIG_DM_MMC */
732