1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
4 */
5
6 #include <common.h>
7 #include <clk.h>
8 #include <fdtdec.h>
9 #include <mmc.h>
10 #include <dm.h>
11 #include <linux/compat.h>
12 #include <linux/dma-direction.h>
13 #include <linux/io.h>
14 #include <linux/sizes.h>
15 #include <power/regulator.h>
16 #include <asm/unaligned.h>
17
18 #include "tmio-common.h"
19
20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
21 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
22 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
23
24 /* SCC registers */
25 #define RENESAS_SDHI_SCC_DTCNTL 0x800
26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
29 #define RENESAS_SDHI_SCC_TAPSET 0x804
30 #define RENESAS_SDHI_SCC_DT2FF 0x808
31 #define RENESAS_SDHI_SCC_CKSEL 0x80c
32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
33 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
35 #define RENESAS_SDHI_SCC_RVSREQ 0x814
36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
37 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
38 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
39 #define RENESAS_SDHI_SCC_SMPCMP 0x818
40 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
41 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
42 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
43 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
44 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
45 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
46 #define RENESAS_SDHI_SCC_TMPPORT3 0x828
47 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
48 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
49 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
50 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
51 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
52 #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
53 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
54 #define RENESAS_SDHI_SCC_TMPPORT5 0x830
55 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
56 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
57 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
58 #define RENESAS_SDHI_SCC_TMPPORT6 0x834
59 #define RENESAS_SDHI_SCC_TMPPORT7 0x838
60 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
61 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
62 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
63
64 #define RENESAS_SDHI_MAX_TAP 3
65
66 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
67
68 static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
69 { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
70 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
71 { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
72 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
73 };
74
75 static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
76 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
77 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
78 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
79 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
80 };
81
82 static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
83 { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
84 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
85 { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
86 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
87 };
88
89 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
90 { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
91 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
92 { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
93 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
94 };
95
96 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
97 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
98 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
99 { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
100 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
101 };
102
rmobile_is_gen3_mmc0(struct tmio_sd_priv * priv)103 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
104 {
105 /* On R-Car Gen3, MMC0 is at 0xee140000 */
106 return (uintptr_t)(priv->regbase) == 0xee140000;
107 }
108
sd_scc_tmpport_read32(struct tmio_sd_priv * priv,u32 addr)109 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
110 {
111 /* read mode */
112 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
113 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
114 RENESAS_SDHI_SCC_TMPPORT5);
115
116 /* access start and stop */
117 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
118 RENESAS_SDHI_SCC_TMPPORT4);
119 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
120
121 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
122 }
123
sd_scc_tmpport_write32(struct tmio_sd_priv * priv,u32 addr,u32 val)124 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
125 {
126 /* write mode */
127 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
128 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
129 RENESAS_SDHI_SCC_TMPPORT5);
130 tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
131
132 /* access start and stop */
133 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
134 RENESAS_SDHI_SCC_TMPPORT4);
135 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
136 }
137
renesas_sdhi_check_scc_error(struct udevice * dev)138 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
139 {
140 struct tmio_sd_priv *priv = dev_get_priv(dev);
141 struct mmc *mmc = mmc_get_mmc_dev(dev);
142 unsigned long new_tap = priv->tap_set;
143 unsigned long error_tap = priv->tap_set;
144 u32 reg, smpcmp;
145
146 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
147 (mmc->selected_mode != UHS_SDR104) &&
148 (mmc->selected_mode != MMC_HS_200) &&
149 (mmc->selected_mode != MMC_HS_400) &&
150 (priv->nrtaps != 4))
151 return false;
152
153 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
154 /* Handle automatic tuning correction */
155 if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
156 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
157 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
158 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
159 return true;
160 }
161
162 return false;
163 }
164
165 /* Handle manual tuning correction */
166 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
167 if (!reg) /* No error */
168 return false;
169
170 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
171
172 if (mmc->selected_mode == MMC_HS_400) {
173 /*
174 * Correction Error Status contains CMD and DAT signal status.
175 * In HS400, DAT signal based on DS signal, not CLK.
176 * Therefore, use only CMD status.
177 */
178 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
179 RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
180
181 switch (smpcmp) {
182 case 0:
183 return false; /* No error in CMD signal */
184 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
185 new_tap = (priv->tap_set +
186 priv->tap_num + 1) % priv->tap_num;
187 error_tap = (priv->tap_set +
188 priv->tap_num - 1) % priv->tap_num;
189 break;
190 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
191 new_tap = (priv->tap_set +
192 priv->tap_num - 1) % priv->tap_num;
193 error_tap = (priv->tap_set +
194 priv->tap_num + 1) % priv->tap_num;
195 break;
196 default:
197 return true; /* Need re-tune */
198 }
199
200 if (priv->hs400_bad_tap & BIT(new_tap)) {
201 /*
202 * New tap is bad tap (cannot change).
203 * Compare with HS200 tuning result.
204 * In HS200 tuning, when smpcmp[error_tap]
205 * is OK, retune is executed.
206 */
207 if (priv->smpcmp & BIT(error_tap))
208 return true; /* Need retune */
209
210 return false; /* cannot change */
211 }
212
213 priv->tap_set = new_tap;
214 } else {
215 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
216 return true; /* Need re-tune */
217 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
218 priv->tap_set = (priv->tap_set +
219 priv->tap_num + 1) % priv->tap_num;
220 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
221 priv->tap_set = (priv->tap_set +
222 priv->tap_num - 1) % priv->tap_num;
223 else
224 return false;
225 }
226
227 /* Set TAP position */
228 tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
229 RENESAS_SDHI_SCC_TAPSET);
230
231 return false;
232 }
233
renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv * priv)234 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
235 {
236 u32 calib_code;
237
238 if (!priv->adjust_hs400_enable)
239 return;
240
241 if (!priv->needs_adjust_hs400)
242 return;
243
244 if (!priv->adjust_hs400_calib_table)
245 return;
246
247 /*
248 * Enabled Manual adjust HS400 mode
249 *
250 * 1) Disabled Write Protect
251 * W(addr=0x00, WP_DISABLE_CODE)
252 *
253 * 2) Read Calibration code
254 * read_value = R(addr=0x26)
255 * 3) Refer to calibration table
256 * Calibration code = table[read_value]
257 * 4) Enabled Manual Calibration
258 * W(addr=0x22, manual mode | Calibration code)
259 * 5) Set Offset value to TMPPORT3 Reg
260 */
261 sd_scc_tmpport_write32(priv, 0x00,
262 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
263 calib_code = sd_scc_tmpport_read32(priv, 0x26);
264 calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
265 sd_scc_tmpport_write32(priv, 0x22,
266 RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
267 priv->adjust_hs400_calib_table[calib_code]);
268 tmio_sd_writel(priv, priv->adjust_hs400_offset,
269 RENESAS_SDHI_SCC_TMPPORT3);
270
271 /* Clear flag */
272 priv->needs_adjust_hs400 = false;
273 }
274
renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv * priv)275 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
276 {
277
278 /* Disabled Manual adjust HS400 mode
279 *
280 * 1) Disabled Write Protect
281 * W(addr=0x00, WP_DISABLE_CODE)
282 * 2) Disabled Manual Calibration
283 * W(addr=0x22, 0)
284 * 3) Clear offset value to TMPPORT3 Reg
285 */
286 sd_scc_tmpport_write32(priv, 0x00,
287 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
288 sd_scc_tmpport_write32(priv, 0x22, 0);
289 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
290 }
291
renesas_sdhi_init_tuning(struct tmio_sd_priv * priv)292 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
293 {
294 u32 reg;
295
296 /* Initialize SCC */
297 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
298
299 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
300 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
301 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
302
303 /* Set sampling clock selection range */
304 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
305 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
306 RENESAS_SDHI_SCC_DTCNTL);
307
308 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
309 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
310 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
311
312 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
313 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
314 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
315
316 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
317 RENESAS_SDHI_SCC_DT2FF);
318
319 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
320 reg |= TMIO_SD_CLKCTL_SCLKEN;
321 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
322
323 /* Read TAPNUM */
324 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
325 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
326 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
327 }
328
renesas_sdhi_reset_tuning(struct tmio_sd_priv * priv)329 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
330 {
331 u32 reg;
332
333 /* Reset SCC */
334 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
335 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
336 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
337
338 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
339 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
340 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
341
342 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
343 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
344 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
345 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
346
347 /* Disable HS400 mode adjustment */
348 renesas_sdhi_adjust_hs400_mode_disable(priv);
349
350 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
351 reg |= TMIO_SD_CLKCTL_SCLKEN;
352 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
353
354 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
355 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
356 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
357
358 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
359 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
360 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
361 }
362
renesas_sdhi_hs400(struct udevice * dev)363 static int renesas_sdhi_hs400(struct udevice *dev)
364 {
365 struct tmio_sd_priv *priv = dev_get_priv(dev);
366 struct mmc *mmc = mmc_get_mmc_dev(dev);
367 bool hs400 = (mmc->selected_mode == MMC_HS_400);
368 int ret, taps = hs400 ? priv->nrtaps : 8;
369 unsigned long new_tap;
370 u32 reg;
371
372 if (taps == 4) /* HS400 on 4tap SoC needs different clock */
373 ret = clk_set_rate(&priv->clk, 400000000);
374 else
375 ret = clk_set_rate(&priv->clk, 200000000);
376 if (ret < 0)
377 return ret;
378
379 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
380 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
381 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
382
383 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
384 if (hs400) {
385 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
386 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
387 } else {
388 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
389 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
390 }
391
392 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
393
394 /* Disable HS400 mode adjustment */
395 if (!hs400)
396 renesas_sdhi_adjust_hs400_mode_disable(priv);
397
398 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
399 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
400 RENESAS_SDHI_SCC_DTCNTL);
401
402 /* Avoid bad TAP */
403 if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
404 new_tap = (priv->tap_set +
405 priv->tap_num + 1) % priv->tap_num;
406
407 if (priv->hs400_bad_tap & BIT(new_tap))
408 new_tap = (priv->tap_set +
409 priv->tap_num - 1) % priv->tap_num;
410
411 if (priv->hs400_bad_tap & BIT(new_tap)) {
412 new_tap = priv->tap_set;
413 debug("Three consecutive bad tap is prohibited\n");
414 }
415
416 priv->tap_set = new_tap;
417 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
418 }
419
420 if (taps == 4) {
421 tmio_sd_writel(priv, priv->tap_set >> 1,
422 RENESAS_SDHI_SCC_TAPSET);
423 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
424 RENESAS_SDHI_SCC_DT2FF);
425 } else {
426 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
427 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
428 }
429
430 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
431 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
432 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
433
434 /* Execute adjust hs400 offset after setting to HS400 mode */
435 if (hs400)
436 priv->needs_adjust_hs400 = true;
437
438 return 0;
439 }
440
renesas_sdhi_prepare_tuning(struct tmio_sd_priv * priv,unsigned long tap)441 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
442 unsigned long tap)
443 {
444 /* Set sampling clock position */
445 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
446 }
447
renesas_sdhi_compare_scc_data(struct tmio_sd_priv * priv)448 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
449 {
450 /* Get comparison of sampling data */
451 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
452 }
453
renesas_sdhi_select_tuning(struct tmio_sd_priv * priv,unsigned int taps)454 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
455 unsigned int taps)
456 {
457 unsigned long tap_cnt; /* counter of tuning success */
458 unsigned long tap_start;/* start position of tuning success */
459 unsigned long tap_end; /* end position of tuning success */
460 unsigned long ntap; /* temporary counter of tuning success */
461 unsigned long match_cnt;/* counter of matching data */
462 unsigned long i;
463 bool select = false;
464 u32 reg;
465
466 priv->needs_adjust_hs400 = false;
467
468 /* Clear SCC_RVSREQ */
469 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
470
471 /* Merge the results */
472 for (i = 0; i < priv->tap_num * 2; i++) {
473 if (!(taps & BIT(i))) {
474 taps &= ~BIT(i % priv->tap_num);
475 taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
476 }
477 if (!(priv->smpcmp & BIT(i))) {
478 priv->smpcmp &= ~BIT(i % priv->tap_num);
479 priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
480 }
481 }
482
483 /*
484 * Find the longest consecutive run of successful probes. If that
485 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
486 * center index as the tap.
487 */
488 tap_cnt = 0;
489 ntap = 0;
490 tap_start = 0;
491 tap_end = 0;
492 for (i = 0; i < priv->tap_num * 2; i++) {
493 if (taps & BIT(i))
494 ntap++;
495 else {
496 if (ntap > tap_cnt) {
497 tap_start = i - ntap;
498 tap_end = i - 1;
499 tap_cnt = ntap;
500 }
501 ntap = 0;
502 }
503 }
504
505 if (ntap > tap_cnt) {
506 tap_start = i - ntap;
507 tap_end = i - 1;
508 tap_cnt = ntap;
509 }
510
511 /*
512 * If all of the TAP is OK, the sampling clock position is selected by
513 * identifying the change point of data.
514 */
515 if (tap_cnt == priv->tap_num * 2) {
516 match_cnt = 0;
517 ntap = 0;
518 tap_start = 0;
519 tap_end = 0;
520 for (i = 0; i < priv->tap_num * 2; i++) {
521 if (priv->smpcmp & BIT(i))
522 ntap++;
523 else {
524 if (ntap > match_cnt) {
525 tap_start = i - ntap;
526 tap_end = i - 1;
527 match_cnt = ntap;
528 }
529 ntap = 0;
530 }
531 }
532 if (ntap > match_cnt) {
533 tap_start = i - ntap;
534 tap_end = i - 1;
535 match_cnt = ntap;
536 }
537 if (match_cnt)
538 select = true;
539 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
540 select = true;
541
542 if (select)
543 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
544 else
545 return -EIO;
546
547 /* Set SCC */
548 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
549
550 /* Enable auto re-tuning */
551 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
552 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
553 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
554
555 return 0;
556 }
557
renesas_sdhi_execute_tuning(struct udevice * dev,uint opcode)558 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
559 {
560 struct tmio_sd_priv *priv = dev_get_priv(dev);
561 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
562 struct mmc *mmc = upriv->mmc;
563 unsigned int tap_num;
564 unsigned int taps = 0;
565 int i, ret = 0;
566 u32 caps;
567
568 /* Only supported on Renesas RCar */
569 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
570 return -EINVAL;
571
572 /* clock tuning is not needed for upto 52MHz */
573 if (!((mmc->selected_mode == MMC_HS_200) ||
574 (mmc->selected_mode == MMC_HS_400) ||
575 (mmc->selected_mode == UHS_SDR104) ||
576 (mmc->selected_mode == UHS_SDR50)))
577 return 0;
578
579 tap_num = renesas_sdhi_init_tuning(priv);
580 if (!tap_num)
581 /* Tuning is not supported */
582 goto out;
583
584 priv->tap_num = tap_num;
585
586 if (priv->tap_num * 2 >= sizeof(taps) * 8) {
587 dev_err(dev,
588 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
589 goto out;
590 }
591
592 priv->smpcmp = 0;
593
594 /* Issue CMD19 twice for each tap */
595 for (i = 0; i < 2 * priv->tap_num; i++) {
596 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
597
598 /* Force PIO for the tuning */
599 caps = priv->caps;
600 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
601
602 ret = mmc_send_tuning(mmc, opcode, NULL);
603
604 priv->caps = caps;
605
606 if (ret == 0)
607 taps |= BIT(i);
608
609 ret = renesas_sdhi_compare_scc_data(priv);
610 if (ret == 0)
611 priv->smpcmp |= BIT(i);
612
613 mdelay(1);
614 }
615
616 ret = renesas_sdhi_select_tuning(priv, taps);
617
618 out:
619 if (ret < 0) {
620 dev_warn(dev, "Tuning procedure failed\n");
621 renesas_sdhi_reset_tuning(priv);
622 }
623
624 return ret;
625 }
626 #else
renesas_sdhi_hs400(struct udevice * dev)627 static int renesas_sdhi_hs400(struct udevice *dev)
628 {
629 return 0;
630 }
631 #endif
632
renesas_sdhi_set_ios(struct udevice * dev)633 static int renesas_sdhi_set_ios(struct udevice *dev)
634 {
635 struct tmio_sd_priv *priv = dev_get_priv(dev);
636 u32 tmp;
637 int ret;
638
639 /* Stop the clock before changing its rate to avoid a glitch signal */
640 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
641 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
642 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
643
644 ret = renesas_sdhi_hs400(dev);
645 if (ret)
646 return ret;
647
648 ret = tmio_sd_set_ios(dev);
649
650 mdelay(10);
651
652 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
653 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
654 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
655 struct mmc *mmc = mmc_get_mmc_dev(dev);
656 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
657 (mmc->selected_mode != UHS_SDR104) &&
658 (mmc->selected_mode != MMC_HS_200) &&
659 (mmc->selected_mode != MMC_HS_400)) {
660 renesas_sdhi_reset_tuning(priv);
661 }
662 #endif
663
664 return ret;
665 }
666
667 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
renesas_sdhi_wait_dat0(struct udevice * dev,int state,int timeout_us)668 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
669 int timeout_us)
670 {
671 int ret = -ETIMEDOUT;
672 bool dat0_high;
673 bool target_dat0_high = !!state;
674 struct tmio_sd_priv *priv = dev_get_priv(dev);
675
676 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
677 while (timeout_us--) {
678 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
679 if (dat0_high == target_dat0_high) {
680 ret = 0;
681 break;
682 }
683 udelay(10);
684 }
685
686 return ret;
687 }
688 #endif
689
renesas_sdhi_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)690 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
691 struct mmc_data *data)
692 {
693 int ret;
694
695 ret = tmio_sd_send_cmd(dev, cmd, data);
696 if (ret)
697 return ret;
698
699 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
700 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
701 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
702 struct tmio_sd_priv *priv = dev_get_priv(dev);
703
704 renesas_sdhi_check_scc_error(dev);
705
706 if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
707 renesas_sdhi_adjust_hs400_mode_enable(priv);
708 #endif
709
710 return 0;
711 }
712
713 static const struct dm_mmc_ops renesas_sdhi_ops = {
714 .send_cmd = renesas_sdhi_send_cmd,
715 .set_ios = renesas_sdhi_set_ios,
716 .get_cd = tmio_sd_get_cd,
717 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
718 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
719 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
720 .execute_tuning = renesas_sdhi_execute_tuning,
721 #endif
722 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
723 .wait_dat0 = renesas_sdhi_wait_dat0,
724 #endif
725 };
726
727 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
728 #define RENESAS_GEN3_QUIRKS \
729 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
730
731 static const struct udevice_id renesas_sdhi_match[] = {
732 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
733 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
734 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
735 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
736 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
737 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
738 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
739 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
740 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
741 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
742 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
743 { /* sentinel */ }
744 };
745
renesas_sdhi_clk_get_rate(struct tmio_sd_priv * priv)746 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
747 {
748 return clk_get_rate(&priv->clk);
749 }
750
renesas_sdhi_filter_caps(struct udevice * dev)751 static void renesas_sdhi_filter_caps(struct udevice *dev)
752 {
753 struct tmio_sd_priv *priv = dev_get_priv(dev);
754
755 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
756 return;
757
758 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
759 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
760 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
761 struct tmio_sd_plat *plat = dev_get_platdata(dev);
762
763 /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
764 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
765 (rmobile_get_cpu_rev_integer() <= 1)) ||
766 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
767 (rmobile_get_cpu_rev_integer() == 1) &&
768 (rmobile_get_cpu_rev_fraction() < 2)))
769 plat->cfg.host_caps &= ~MMC_MODE_HS400;
770
771 /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
772 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
773 (rmobile_get_cpu_rev_integer() >= 2)) ||
774 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
775 (rmobile_get_cpu_rev_integer() == 1) &&
776 (rmobile_get_cpu_rev_fraction() == 2)) ||
777 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
778 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
779
780 /* H3 ES3.0 can use HS400 with manual adjustment */
781 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
782 (rmobile_get_cpu_rev_integer() >= 3)) {
783 priv->adjust_hs400_enable = true;
784 priv->adjust_hs400_offset = 0;
785 priv->adjust_hs400_calib_table =
786 r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
787 }
788
789 /* M3W ES1.2 can use HS400 with manual adjustment */
790 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
791 (rmobile_get_cpu_rev_integer() == 1) &&
792 (rmobile_get_cpu_rev_fraction() == 2)) {
793 priv->adjust_hs400_enable = true;
794 priv->adjust_hs400_offset = 3;
795 priv->adjust_hs400_calib_table =
796 r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
797 }
798
799 /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
800 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
801 (rmobile_get_cpu_rev_integer() == 1) &&
802 (rmobile_get_cpu_rev_fraction() > 2)) {
803 priv->adjust_hs400_enable = true;
804 priv->adjust_hs400_offset = 0;
805 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
806 priv->adjust_hs400_calib_table =
807 r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
808 }
809
810 /* M3N can use HS400 with manual adjustment */
811 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
812 priv->adjust_hs400_enable = true;
813 priv->adjust_hs400_offset = 3;
814 priv->adjust_hs400_calib_table =
815 r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
816 }
817
818 /* E3 can use HS400 with manual adjustment */
819 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
820 priv->adjust_hs400_enable = true;
821 priv->adjust_hs400_offset = 3;
822 priv->adjust_hs400_calib_table =
823 r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
824 }
825
826 /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
827 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
828 (rmobile_get_cpu_rev_integer() <= 2)) ||
829 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
830 (rmobile_get_cpu_rev_integer() == 1) &&
831 (rmobile_get_cpu_rev_fraction() <= 2)))
832 priv->nrtaps = 4;
833 else
834 priv->nrtaps = 8;
835 #endif
836 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
837 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
838 (rmobile_get_cpu_rev_integer() <= 1)) ||
839 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
840 (rmobile_get_cpu_rev_integer() == 1) &&
841 (rmobile_get_cpu_rev_fraction() == 0)))
842 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
843 else
844 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
845 }
846
renesas_sdhi_probe(struct udevice * dev)847 static int renesas_sdhi_probe(struct udevice *dev)
848 {
849 struct tmio_sd_priv *priv = dev_get_priv(dev);
850 u32 quirks = dev_get_driver_data(dev);
851 struct fdt_resource reg_res;
852 DECLARE_GLOBAL_DATA_PTR;
853 int ret;
854
855 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
856
857 if (quirks == RENESAS_GEN2_QUIRKS) {
858 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
859 "reg", 0, ®_res);
860 if (ret < 0) {
861 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
862 ret);
863 return ret;
864 }
865
866 if (fdt_resource_size(®_res) == 0x100)
867 quirks |= TMIO_SD_CAP_16BIT;
868 }
869
870 ret = clk_get_by_index(dev, 0, &priv->clk);
871 if (ret < 0) {
872 dev_err(dev, "failed to get host clock\n");
873 return ret;
874 }
875
876 /* set to max rate */
877 ret = clk_set_rate(&priv->clk, 200000000);
878 if (ret < 0) {
879 dev_err(dev, "failed to set rate for host clock\n");
880 clk_free(&priv->clk);
881 return ret;
882 }
883
884 ret = clk_enable(&priv->clk);
885 if (ret) {
886 dev_err(dev, "failed to enable host clock\n");
887 return ret;
888 }
889
890 ret = tmio_sd_probe(dev, quirks);
891
892 renesas_sdhi_filter_caps(dev);
893
894 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
895 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
896 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
897 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
898 renesas_sdhi_reset_tuning(priv);
899 #endif
900 return ret;
901 }
902
903 U_BOOT_DRIVER(renesas_sdhi) = {
904 .name = "renesas-sdhi",
905 .id = UCLASS_MMC,
906 .of_match = renesas_sdhi_match,
907 .bind = tmio_sd_bind,
908 .probe = renesas_sdhi_probe,
909 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
910 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
911 .ops = &renesas_sdhi_ops,
912 };
913