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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2017 Socionext Inc.
4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5  */
6 
7 #include <clk.h>
8 #include <dm.h>
9 #include <linux/io.h>
10 #include <linux/ioport.h>
11 #include <linux/printk.h>
12 
13 #include "denali.h"
14 
15 struct denali_dt_data {
16 	unsigned int revision;
17 	unsigned int caps;
18 	const struct nand_ecc_caps *ecc_caps;
19 };
20 
21 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
22 		     512, 8, 15);
23 static const struct denali_dt_data denali_socfpga_data = {
24 	.caps = DENALI_CAP_HW_ECC_FIXUP,
25 	.ecc_caps = &denali_socfpga_ecc_caps,
26 };
27 
28 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
29 		     1024, 8, 16, 24);
30 static const struct denali_dt_data denali_uniphier_v5a_data = {
31 	.caps = DENALI_CAP_HW_ECC_FIXUP |
32 		DENALI_CAP_DMA_64BIT,
33 	.ecc_caps = &denali_uniphier_v5a_ecc_caps,
34 };
35 
36 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
37 		     1024, 8, 16);
38 static const struct denali_dt_data denali_uniphier_v5b_data = {
39 	.revision = 0x0501,
40 	.caps = DENALI_CAP_HW_ECC_FIXUP |
41 		DENALI_CAP_DMA_64BIT,
42 	.ecc_caps = &denali_uniphier_v5b_ecc_caps,
43 };
44 
45 static const struct udevice_id denali_nand_dt_ids[] = {
46 	{
47 		.compatible = "altr,socfpga-denali-nand",
48 		.data = (unsigned long)&denali_socfpga_data,
49 	},
50 	{
51 		.compatible = "socionext,uniphier-denali-nand-v5a",
52 		.data = (unsigned long)&denali_uniphier_v5a_data,
53 	},
54 	{
55 		.compatible = "socionext,uniphier-denali-nand-v5b",
56 		.data = (unsigned long)&denali_uniphier_v5b_data,
57 	},
58 	{ /* sentinel */ }
59 };
60 
denali_dt_probe(struct udevice * dev)61 static int denali_dt_probe(struct udevice *dev)
62 {
63 	struct denali_nand_info *denali = dev_get_priv(dev);
64 	const struct denali_dt_data *data;
65 	struct clk clk, clk_x, clk_ecc;
66 	struct resource res;
67 	int ret;
68 
69 	data = (void *)dev_get_driver_data(dev);
70 	if (data) {
71 		denali->revision = data->revision;
72 		denali->caps = data->caps;
73 		denali->ecc_caps = data->ecc_caps;
74 	}
75 
76 	denali->dev = dev;
77 
78 	ret = dev_read_resource_byname(dev, "denali_reg", &res);
79 	if (ret)
80 		return ret;
81 
82 	denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
83 
84 	ret = dev_read_resource_byname(dev, "nand_data", &res);
85 	if (ret)
86 		return ret;
87 
88 	denali->host = devm_ioremap(dev, res.start, resource_size(&res));
89 
90 	ret = clk_get_by_name(dev, "nand", &clk);
91 	if (ret)
92 		ret = clk_get_by_index(dev, 0, &clk);
93 	if (ret)
94 		return ret;
95 
96 	ret = clk_get_by_name(dev, "nand_x", &clk_x);
97 	if (ret)
98 		clk_x.dev = NULL;
99 
100 	ret = clk_get_by_name(dev, "ecc", &clk_ecc);
101 	if (ret)
102 		clk_ecc.dev = NULL;
103 
104 	ret = clk_enable(&clk);
105 	if (ret)
106 		return ret;
107 
108 	if (clk_x.dev) {
109 		ret = clk_enable(&clk_x);
110 		if (ret)
111 			return ret;
112 	}
113 
114 	if (clk_ecc.dev) {
115 		ret = clk_enable(&clk_ecc);
116 		if (ret)
117 			return ret;
118 	}
119 
120 	if (clk_x.dev) {
121 		denali->clk_rate = clk_get_rate(&clk);
122 		denali->clk_x_rate = clk_get_rate(&clk_x);
123 	} else {
124 		/*
125 		 * Hardcode the clock rates for the backward compatibility.
126 		 * This works for both SOCFPGA and UniPhier.
127 		 */
128 		dev_notice(dev,
129 			   "necessary clock is missing. default clock rates are used.\n");
130 		denali->clk_rate = 50000000;
131 		denali->clk_x_rate = 200000000;
132 	}
133 
134 	ret = reset_get_bulk(dev, &denali->resets);
135 	if (ret)
136 		dev_warn(dev, "Can't get reset: %d\n", ret);
137 	else
138 		reset_deassert_bulk(&denali->resets);
139 
140 	return denali_init(denali);
141 }
142 
denali_dt_remove(struct udevice * dev)143 static int denali_dt_remove(struct udevice *dev)
144 {
145 	struct denali_nand_info *denali = dev_get_priv(dev);
146 
147 	return reset_release_bulk(&denali->resets);
148 }
149 
150 U_BOOT_DRIVER(denali_nand_dt) = {
151 	.name = "denali-nand-dt",
152 	.id = UCLASS_MISC,
153 	.of_match = denali_nand_dt_ids,
154 	.probe = denali_dt_probe,
155 	.priv_auto_alloc_size = sizeof(struct denali_nand_info),
156 	.remove = denali_dt_remove,
157 	.flags = DM_FLAG_OS_PREPARE,
158 };
159 
board_nand_init(void)160 void board_nand_init(void)
161 {
162 	struct udevice *dev;
163 	int ret;
164 
165 	ret = uclass_get_device_by_driver(UCLASS_MISC,
166 					  DM_GET_DRIVER(denali_nand_dt),
167 					  &dev);
168 	if (ret && ret != -ENODEV)
169 		pr_err("Failed to initialize Denali NAND controller. (error %d)\n",
170 		       ret);
171 }
172