1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 */
6 #include <common.h>
7 #include <env.h>
8 #include <malloc.h>
9 #include <asm/io.h>
10 #include <linux/errno.h>
11 #include <u-boot/crc.h>
12
13 #include "fm.h"
14 #include <fsl_qe.h> /* For struct qe_firmware */
15
16 #include <nand.h>
17 #include <spi_flash.h>
18 #include <mmc.h>
19
20 #ifdef CONFIG_ARM64
21 #include <asm/armv8/mmu.h>
22 #include <asm/arch/cpu.h>
23 #endif
24
25 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
26
fm_muram_base(int fm_idx)27 void *fm_muram_base(int fm_idx)
28 {
29 return muram[fm_idx].base;
30 }
31
fm_muram_alloc(int fm_idx,size_t size,ulong align)32 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
33 {
34 void *ret;
35 ulong align_mask;
36 size_t off;
37 void *save;
38
39 align_mask = align - 1;
40 save = muram[fm_idx].alloc;
41
42 off = (ulong)save & align_mask;
43 if (off != 0)
44 muram[fm_idx].alloc += (align - off);
45 off = size & align_mask;
46 if (off != 0)
47 size += (align - off);
48 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
49 muram[fm_idx].alloc = save;
50 printf("%s: run out of ram.\n", __func__);
51 return NULL;
52 }
53
54 ret = muram[fm_idx].alloc;
55 muram[fm_idx].alloc += size;
56 memset((void *)ret, 0, size);
57
58 return ret;
59 }
60
fm_init_muram(int fm_idx,void * reg)61 static void fm_init_muram(int fm_idx, void *reg)
62 {
63 void *base = reg;
64
65 muram[fm_idx].base = base;
66 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
67 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
68 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
69 }
70
71 /*
72 * fm_upload_ucode - Fman microcode upload worker function
73 *
74 * This function does the actual uploading of an Fman microcode
75 * to an Fman.
76 */
fm_upload_ucode(int fm_idx,struct fm_imem * imem,u32 * ucode,unsigned int size)77 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
78 u32 *ucode, unsigned int size)
79 {
80 unsigned int i;
81 unsigned int timeout = 1000000;
82
83 /* enable address auto increase */
84 out_be32(&imem->iadd, IRAM_IADD_AIE);
85 /* write microcode to IRAM */
86 for (i = 0; i < size / 4; i++)
87 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
88
89 /* verify if the writing is over */
90 out_be32(&imem->iadd, 0);
91 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
92 ;
93 if (!timeout)
94 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
95
96 /* enable microcode from IRAM */
97 out_be32(&imem->iready, IRAM_READY);
98 }
99
100 /*
101 * Upload an Fman firmware
102 *
103 * This function is similar to qe_upload_firmware(), exception that it uploads
104 * a microcode to the Fman instead of the QE.
105 *
106 * Because the process for uploading a microcode to the Fman is similar for
107 * that of the QE, the QE firmware binary format is used for Fman microcode.
108 * It should be possible to unify these two functions, but for now we keep them
109 * separate.
110 */
fman_upload_firmware(int fm_idx,struct fm_imem * fm_imem,const struct qe_firmware * firmware)111 static int fman_upload_firmware(int fm_idx,
112 struct fm_imem *fm_imem,
113 const struct qe_firmware *firmware)
114 {
115 unsigned int i;
116 u32 crc;
117 size_t calc_size = sizeof(struct qe_firmware);
118 size_t length;
119 const struct qe_header *hdr;
120
121 if (!firmware) {
122 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
123 return -EINVAL;
124 }
125
126 hdr = &firmware->header;
127 length = be32_to_cpu(hdr->length);
128
129 /* Check the magic */
130 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
131 (hdr->magic[2] != 'F')) {
132 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
133 firmware);
134 return -EPERM;
135 }
136
137 /* Check the version */
138 if (hdr->version != 1) {
139 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
140 hdr->version);
141 return -EPERM;
142 }
143
144 /* Validate some of the fields */
145 if ((firmware->count != 1)) {
146 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
147 return -EINVAL;
148 }
149
150 /* Validate the length and check if there's a CRC */
151 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
152
153 for (i = 0; i < firmware->count; i++)
154 /*
155 * For situations where the second RISC uses the same microcode
156 * as the first, the 'code_offset' and 'count' fields will be
157 * zero, so it's okay to add those.
158 */
159 calc_size += sizeof(u32) *
160 be32_to_cpu(firmware->microcode[i].count);
161
162 /* Validate the length */
163 if (length != calc_size + sizeof(u32)) {
164 printf("Fman%u: Invalid length in firmware header\n",
165 fm_idx + 1);
166 return -EPERM;
167 }
168
169 /*
170 * Validate the CRC. We would normally call crc32_no_comp(), but that
171 * function isn't available unless you turn on JFFS support.
172 */
173 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
174 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
175 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
176 return -EIO;
177 }
178
179 /* Loop through each microcode. */
180 for (i = 0; i < firmware->count; i++) {
181 const struct qe_microcode *ucode = &firmware->microcode[i];
182
183 /* Upload a microcode if it's present */
184 if (be32_to_cpu(ucode->code_offset)) {
185 u32 ucode_size;
186 u32 *code;
187 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
188 fm_idx + 1, ucode->major, ucode->minor,
189 ucode->revision);
190 code = (void *)firmware +
191 be32_to_cpu(ucode->code_offset);
192 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
193 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
194 }
195 }
196
197 return 0;
198 }
199
fm_assign_risc(int port_id)200 static u32 fm_assign_risc(int port_id)
201 {
202 u32 risc_sel, val;
203 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
204 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
205 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
206
207 return val;
208 }
209
fm_init_fpm(struct fm_fpm * fpm)210 static void fm_init_fpm(struct fm_fpm *fpm)
211 {
212 int i, port_id;
213 u32 val;
214
215 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
216 FMFPEE_CER | FMFPEE_DER);
217
218 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
219
220 /* offline/parser port */
221 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
222 port_id = OH_PORT_ID_BASE + i;
223 val = fm_assign_risc(port_id);
224 out_be32(&fpm->fpmprc, val);
225 }
226 /* Rx 1G port */
227 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
228 port_id = RX_PORT_1G_BASE + i;
229 val = fm_assign_risc(port_id);
230 out_be32(&fpm->fpmprc, val);
231 }
232 /* Tx 1G port */
233 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
234 port_id = TX_PORT_1G_BASE + i;
235 val = fm_assign_risc(port_id);
236 out_be32(&fpm->fpmprc, val);
237 }
238 /* Rx 10G port */
239 port_id = RX_PORT_10G_BASE;
240 val = fm_assign_risc(port_id);
241 out_be32(&fpm->fpmprc, val);
242 /* Tx 10G port */
243 port_id = TX_PORT_10G_BASE;
244 val = fm_assign_risc(port_id);
245 out_be32(&fpm->fpmprc, val);
246
247 /* disable the dispatch limit in IM case */
248 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
249 /* clear events */
250 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
251
252 /* clear risc events */
253 for (i = 0; i < 4; i++)
254 out_be32(&fpm->fpmcev[i], 0xffffffff);
255
256 /* clear error */
257 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
258 }
259
fm_init_bmi(int fm_idx,struct fm_bmi_common * bmi)260 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
261 {
262 int blk, i, port_id;
263 u32 val;
264 size_t offset;
265 void *base;
266
267 /* alloc free buffer pool in MURAM */
268 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
269 if (!base) {
270 printf("%s: no muram for free buffer pool\n", __func__);
271 return -ENOMEM;
272 }
273 offset = base - fm_muram_base(fm_idx);
274
275 /* Need 128KB total free buffer pool size */
276 val = offset / 256;
277 blk = FM_FREE_POOL_SIZE / 256;
278 /* in IM, we must not begin from offset 0 in MURAM */
279 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
280 out_be32(&bmi->fmbm_cfg1, val);
281
282 /* disable all BMI interrupt */
283 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
284
285 /* clear all events */
286 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
287
288 /*
289 * set port parameters - FMBM_PP_x
290 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
291 * max dma 10G Rx/Tx=3, others is 1
292 * set port FIFO size - FMBM_PFS_x
293 * 4KB for all Rx and Tx ports
294 */
295 /* offline/parser port */
296 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
297 port_id = OH_PORT_ID_BASE + i - 1;
298 /* max tasks=1, max dma=1, no extra */
299 out_be32(&bmi->fmbm_pp[port_id], 0);
300 /* port FIFO size - 256 bytes, no extra */
301 out_be32(&bmi->fmbm_pfs[port_id], 0);
302 }
303 /* Rx 1G port */
304 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
305 port_id = RX_PORT_1G_BASE + i - 1;
306 /* max tasks=4, max dma=1, no extra */
307 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
308 /* FIFO size - 4KB, no extra */
309 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
310 }
311 /* Tx 1G port FIFO size - 4KB, no extra */
312 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
313 port_id = TX_PORT_1G_BASE + i - 1;
314 /* max tasks=4, max dma=1, no extra */
315 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
316 /* FIFO size - 4KB, no extra */
317 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
318 }
319 /* Rx 10G port */
320 port_id = RX_PORT_10G_BASE - 1;
321 /* max tasks=12, max dma=3, no extra */
322 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
323 /* FIFO size - 4KB, no extra */
324 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
325
326 /* Tx 10G port */
327 port_id = TX_PORT_10G_BASE - 1;
328 /* max tasks=12, max dma=3, no extra */
329 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
330 /* FIFO size - 4KB, no extra */
331 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
332
333 /* initialize internal buffers data base (linked list) */
334 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
335
336 return 0;
337 }
338
fm_init_qmi(struct fm_qmi_common * qmi)339 static void fm_init_qmi(struct fm_qmi_common *qmi)
340 {
341 /* disable all error interrupts */
342 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
343 /* clear all error events */
344 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
345
346 /* disable all interrupts */
347 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
348 /* clear all interrupts */
349 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
350 }
351
352 /* Init common part of FM, index is fm num# like fm as above */
353 #ifdef CONFIG_TFABOOT
fm_init_common(int index,struct ccsr_fman * reg)354 int fm_init_common(int index, struct ccsr_fman *reg)
355 {
356 int rc;
357 void *addr = NULL;
358 enum boot_src src = get_boot_src();
359
360 if (src == BOOT_SOURCE_IFC_NOR) {
361 addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
362 CONFIG_SYS_FSL_IFC_BASE);
363 } else if (src == BOOT_SOURCE_IFC_NAND) {
364 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
365
366 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
367
368 rc = nand_read(get_nand_dev_by_index(0),
369 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
370 &fw_length, (u_char *)addr);
371 if (rc == -EUCLEAN) {
372 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
373 CONFIG_SYS_FMAN_FW_ADDR, rc);
374 }
375 } else if (src == BOOT_SOURCE_QSPI_NOR) {
376 struct spi_flash *ucode_flash;
377
378 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
379 int ret = 0;
380
381 #ifdef CONFIG_DM_SPI_FLASH
382 struct udevice *new;
383
384 /* speed and mode will be read from DT */
385 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
386 CONFIG_ENV_SPI_CS, 0, 0, &new);
387
388 ucode_flash = dev_get_uclass_priv(new);
389 #else
390 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
391 CONFIG_ENV_SPI_CS,
392 CONFIG_ENV_SPI_MAX_HZ,
393 CONFIG_ENV_SPI_MODE);
394 #endif
395 if (!ucode_flash) {
396 printf("SF: probe for ucode failed\n");
397 } else {
398 ret = spi_flash_read(ucode_flash,
399 CONFIG_SYS_FMAN_FW_ADDR +
400 CONFIG_SYS_FSL_QSPI_BASE,
401 CONFIG_SYS_QE_FMAN_FW_LENGTH,
402 addr);
403 if (ret)
404 printf("SF: read for ucode failed\n");
405 spi_flash_free(ucode_flash);
406 }
407 } else if (src == BOOT_SOURCE_SD_MMC) {
408 int dev = CONFIG_SYS_MMC_ENV_DEV;
409
410 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
411 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
412 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
413 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
414
415 if (!mmc) {
416 printf("\nMMC cannot find device for ucode\n");
417 } else {
418 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
419 dev, blk, cnt);
420 mmc_init(mmc);
421 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
422 addr);
423 }
424 } else {
425 addr = NULL;
426 }
427
428 /* Upload the Fman microcode if it's present */
429 rc = fman_upload_firmware(index, ®->fm_imem, addr);
430 if (rc)
431 return rc;
432 env_set_addr("fman_ucode", addr);
433
434 fm_init_muram(index, ®->muram);
435 fm_init_qmi(®->fm_qmi_common);
436 fm_init_fpm(®->fm_fpm);
437
438 /* clear DMA status */
439 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
440
441 /* set DMA mode */
442 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
443
444 return fm_init_bmi(index, ®->fm_bmi_common);
445 }
446 #else
fm_init_common(int index,struct ccsr_fman * reg)447 int fm_init_common(int index, struct ccsr_fman *reg)
448 {
449 int rc;
450 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
451 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
452 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
453 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
454 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
455
456 rc = nand_read(get_nand_dev_by_index(0),
457 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
458 &fw_length, (u_char *)addr);
459 if (rc == -EUCLEAN) {
460 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
461 CONFIG_SYS_FMAN_FW_ADDR, rc);
462 }
463 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
464 struct spi_flash *ucode_flash;
465 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
466 int ret = 0;
467
468 #ifdef CONFIG_DM_SPI_FLASH
469 struct udevice *new;
470
471 /* speed and mode will be read from DT */
472 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
473 0, 0, &new);
474
475 ucode_flash = dev_get_uclass_priv(new);
476 #else
477 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
478 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
479 #endif
480 if (!ucode_flash)
481 printf("SF: probe for ucode failed\n");
482 else {
483 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
484 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
485 if (ret)
486 printf("SF: read for ucode failed\n");
487 spi_flash_free(ucode_flash);
488 }
489 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
490 int dev = CONFIG_SYS_MMC_ENV_DEV;
491 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
492 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
493 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
494 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
495
496 if (!mmc)
497 printf("\nMMC cannot find device for ucode\n");
498 else {
499 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
500 dev, blk, cnt);
501 mmc_init(mmc);
502 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
503 addr);
504 }
505 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
506 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
507 #else
508 void *addr = NULL;
509 #endif
510
511 /* Upload the Fman microcode if it's present */
512 rc = fman_upload_firmware(index, ®->fm_imem, addr);
513 if (rc)
514 return rc;
515 env_set_addr("fman_ucode", addr);
516
517 fm_init_muram(index, ®->muram);
518 fm_init_qmi(®->fm_qmi_common);
519 fm_init_fpm(®->fm_fpm);
520
521 /* clear DMA status */
522 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
523
524 /* set DMA mode */
525 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
526
527 return fm_init_bmi(index, ®->fm_bmi_common);
528 }
529 #endif
530