1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <asm/io.h>
13 #include <pci.h>
14 #include <miiphy.h>
15 #include "pch_gbe.h"
16
17 #if !defined(CONFIG_PHYLIB)
18 # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
19 #endif
20
21 static struct pci_device_id supported[] = {
22 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
23 { }
24 };
25
pch_gbe_mac_read(struct pch_gbe_regs * mac_regs,u8 * addr)26 static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
27 {
28 u32 macid_hi, macid_lo;
29
30 macid_hi = readl(&mac_regs->mac_adr[0].high);
31 macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
32 debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
33
34 addr[0] = (u8)(macid_hi & 0xff);
35 addr[1] = (u8)((macid_hi >> 8) & 0xff);
36 addr[2] = (u8)((macid_hi >> 16) & 0xff);
37 addr[3] = (u8)((macid_hi >> 24) & 0xff);
38 addr[4] = (u8)(macid_lo & 0xff);
39 addr[5] = (u8)((macid_lo >> 8) & 0xff);
40 }
41
pch_gbe_mac_write(struct pch_gbe_regs * mac_regs,u8 * addr)42 static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
43 {
44 u32 macid_hi, macid_lo;
45 ulong start;
46
47 macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
48 macid_lo = addr[4] + (addr[5] << 8);
49
50 writel(macid_hi, &mac_regs->mac_adr[0].high);
51 writel(macid_lo, &mac_regs->mac_adr[0].low);
52 writel(0xfffe, &mac_regs->addr_mask);
53
54 start = get_timer(0);
55 while (get_timer(start) < PCH_GBE_TIMEOUT) {
56 if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
57 return 0;
58
59 udelay(10);
60 }
61
62 return -ETIME;
63 }
64
pch_gbe_reset(struct udevice * dev)65 static int pch_gbe_reset(struct udevice *dev)
66 {
67 struct pch_gbe_priv *priv = dev_get_priv(dev);
68 struct eth_pdata *plat = dev_get_platdata(dev);
69 struct pch_gbe_regs *mac_regs = priv->mac_regs;
70 ulong start;
71
72 priv->rx_idx = 0;
73 priv->tx_idx = 0;
74
75 writel(PCH_GBE_ALL_RST, &mac_regs->reset);
76
77 /*
78 * Configure the MAC to RGMII mode after reset
79 *
80 * For some unknown reason, we must do the configuration here right
81 * after resetting the whole MAC, otherwise the reset bit in the RESET
82 * register will never be cleared by the hardware. And there is another
83 * way of having the same magic, that is to configure the MODE register
84 * to have the MAC work in MII/GMII mode, which is how current Linux
85 * pch_gbe driver does. Since anyway we need program the MAC to RGMII
86 * mode in the driver, we just do it here.
87 *
88 * Note: this behavior is not documented in the hardware manual.
89 */
90 writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
91 &mac_regs->rgmii_ctrl);
92
93 start = get_timer(0);
94 while (get_timer(start) < PCH_GBE_TIMEOUT) {
95 if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
96 /*
97 * Soft reset clears hardware MAC address registers,
98 * so we have to reload MAC address here in order to
99 * make linux pch_gbe driver happy.
100 */
101 return pch_gbe_mac_write(mac_regs, plat->enetaddr);
102 }
103
104 udelay(10);
105 }
106
107 debug("pch_gbe: reset timeout\n");
108 return -ETIME;
109 }
110
pch_gbe_rx_descs_init(struct udevice * dev)111 static void pch_gbe_rx_descs_init(struct udevice *dev)
112 {
113 struct pch_gbe_priv *priv = dev_get_priv(dev);
114 struct pch_gbe_regs *mac_regs = priv->mac_regs;
115 struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
116 int i;
117
118 memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
119 for (i = 0; i < PCH_GBE_DESC_NUM; i++)
120 rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
121 priv->rx_buff[i]);
122
123 flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
124
125 writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
126 &mac_regs->rx_dsc_base);
127 writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
128 &mac_regs->rx_dsc_size);
129
130 writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
131 &mac_regs->rx_dsc_sw_p);
132 }
133
pch_gbe_tx_descs_init(struct udevice * dev)134 static void pch_gbe_tx_descs_init(struct udevice *dev)
135 {
136 struct pch_gbe_priv *priv = dev_get_priv(dev);
137 struct pch_gbe_regs *mac_regs = priv->mac_regs;
138 struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
139
140 memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
141
142 flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
143
144 writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
145 &mac_regs->tx_dsc_base);
146 writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
147 &mac_regs->tx_dsc_size);
148 writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
149 &mac_regs->tx_dsc_sw_p);
150 }
151
pch_gbe_adjust_link(struct pch_gbe_regs * mac_regs,struct phy_device * phydev)152 static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
153 struct phy_device *phydev)
154 {
155 if (!phydev->link) {
156 printf("%s: No link.\n", phydev->dev->name);
157 return;
158 }
159
160 clrbits_le32(&mac_regs->rgmii_ctrl,
161 PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
162 clrbits_le32(&mac_regs->mode,
163 PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
164
165 switch (phydev->speed) {
166 case 1000:
167 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
168 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
169 break;
170 case 100:
171 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
172 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
173 break;
174 case 10:
175 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
176 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
177 break;
178 }
179
180 if (phydev->duplex) {
181 setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
182 setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
183 }
184
185 printf("Speed: %d, %s duplex\n", phydev->speed,
186 (phydev->duplex) ? "full" : "half");
187
188 return;
189 }
190
pch_gbe_start(struct udevice * dev)191 static int pch_gbe_start(struct udevice *dev)
192 {
193 struct pch_gbe_priv *priv = dev_get_priv(dev);
194 struct pch_gbe_regs *mac_regs = priv->mac_regs;
195
196 if (pch_gbe_reset(dev))
197 return -1;
198
199 pch_gbe_rx_descs_init(dev);
200 pch_gbe_tx_descs_init(dev);
201
202 /* Enable frame bursting */
203 writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
204 /* Disable TCP/IP accelerator */
205 writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
206 /* Disable RX flow control */
207 writel(0, &mac_regs->rx_fctrl);
208 /* Configure RX/TX mode */
209 writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
210 PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
211 writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
212 PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
213 PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
214
215 /* Start up the PHY */
216 if (phy_startup(priv->phydev)) {
217 printf("Could not initialize PHY %s\n",
218 priv->phydev->dev->name);
219 return -1;
220 }
221
222 pch_gbe_adjust_link(mac_regs, priv->phydev);
223
224 if (!priv->phydev->link)
225 return -1;
226
227 /* Enable TX & RX */
228 writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
229 writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
230
231 return 0;
232 }
233
pch_gbe_stop(struct udevice * dev)234 static void pch_gbe_stop(struct udevice *dev)
235 {
236 struct pch_gbe_priv *priv = dev_get_priv(dev);
237
238 pch_gbe_reset(dev);
239
240 phy_shutdown(priv->phydev);
241 }
242
pch_gbe_send(struct udevice * dev,void * packet,int length)243 static int pch_gbe_send(struct udevice *dev, void *packet, int length)
244 {
245 struct pch_gbe_priv *priv = dev_get_priv(dev);
246 struct pch_gbe_regs *mac_regs = priv->mac_regs;
247 struct pch_gbe_tx_desc *tx_head, *tx_desc;
248 u16 frame_ctrl = 0;
249 u32 int_st;
250 ulong start;
251
252 flush_dcache_range((ulong)packet, (ulong)packet + length);
253
254 tx_head = &priv->tx_desc[0];
255 tx_desc = &priv->tx_desc[priv->tx_idx];
256
257 if (length < 64)
258 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
259
260 tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
261 tx_desc->length = length;
262 tx_desc->tx_words_eob = length + 3;
263 tx_desc->tx_frame_ctrl = frame_ctrl;
264 tx_desc->dma_status = 0;
265 tx_desc->gbec_status = 0;
266
267 flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
268
269 /* Test the wrap-around condition */
270 if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
271 priv->tx_idx = 0;
272
273 writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
274 &mac_regs->tx_dsc_sw_p);
275
276 start = get_timer(0);
277 while (get_timer(start) < PCH_GBE_TIMEOUT) {
278 int_st = readl(&mac_regs->int_st);
279 if (int_st & PCH_GBE_INT_TX_CMPLT)
280 return 0;
281
282 udelay(10);
283 }
284
285 debug("pch_gbe: sent failed\n");
286 return -ETIME;
287 }
288
pch_gbe_recv(struct udevice * dev,int flags,uchar ** packetp)289 static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
290 {
291 struct pch_gbe_priv *priv = dev_get_priv(dev);
292 struct pch_gbe_regs *mac_regs = priv->mac_regs;
293 struct pch_gbe_rx_desc *rx_desc;
294 ulong hw_desc, length;
295 void *buffer;
296
297 rx_desc = &priv->rx_desc[priv->rx_idx];
298
299 readl(&mac_regs->int_st);
300 hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
301
302 /* Just return if not receiving any packet */
303 if (virt_to_phys(rx_desc) == hw_desc)
304 return -EAGAIN;
305
306 /* Invalidate the descriptor */
307 invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
308
309 length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
310 buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
311 invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
312 *packetp = (uchar *)buffer;
313
314 return length;
315 }
316
pch_gbe_free_pkt(struct udevice * dev,uchar * packet,int length)317 static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
318 {
319 struct pch_gbe_priv *priv = dev_get_priv(dev);
320 struct pch_gbe_regs *mac_regs = priv->mac_regs;
321 struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
322 int rx_swp;
323
324 /* Test the wrap-around condition */
325 if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
326 priv->rx_idx = 0;
327 rx_swp = priv->rx_idx;
328 if (++rx_swp >= PCH_GBE_DESC_NUM)
329 rx_swp = 0;
330
331 writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
332 &mac_regs->rx_dsc_sw_p);
333
334 return 0;
335 }
336
pch_gbe_mdio_ready(struct pch_gbe_regs * mac_regs)337 static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
338 {
339 ulong start = get_timer(0);
340
341 while (get_timer(start) < PCH_GBE_TIMEOUT) {
342 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
343 return 0;
344
345 udelay(10);
346 }
347
348 return -ETIME;
349 }
350
pch_gbe_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)351 static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
352 {
353 struct pch_gbe_regs *mac_regs = bus->priv;
354 u32 miim;
355
356 if (pch_gbe_mdio_ready(mac_regs))
357 return -ETIME;
358
359 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
360 (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
361 PCH_GBE_MIIM_OPER_READ;
362 writel(miim, &mac_regs->miim);
363
364 if (pch_gbe_mdio_ready(mac_regs))
365 return -ETIME;
366
367 return readl(&mac_regs->miim) & 0xffff;
368 }
369
pch_gbe_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)370 static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
371 int reg, u16 val)
372 {
373 struct pch_gbe_regs *mac_regs = bus->priv;
374 u32 miim;
375
376 if (pch_gbe_mdio_ready(mac_regs))
377 return -ETIME;
378
379 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
380 (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
381 PCH_GBE_MIIM_OPER_WRITE | val;
382 writel(miim, &mac_regs->miim);
383
384 if (pch_gbe_mdio_ready(mac_regs))
385 return -ETIME;
386 else
387 return 0;
388 }
389
pch_gbe_mdio_init(const char * name,struct pch_gbe_regs * mac_regs)390 static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
391 {
392 struct mii_dev *bus;
393
394 bus = mdio_alloc();
395 if (!bus) {
396 debug("pch_gbe: failed to allocate MDIO bus\n");
397 return -ENOMEM;
398 }
399
400 bus->read = pch_gbe_mdio_read;
401 bus->write = pch_gbe_mdio_write;
402 strcpy(bus->name, name);
403
404 bus->priv = (void *)mac_regs;
405
406 return mdio_register(bus);
407 }
408
pch_gbe_phy_init(struct udevice * dev)409 static int pch_gbe_phy_init(struct udevice *dev)
410 {
411 struct pch_gbe_priv *priv = dev_get_priv(dev);
412 struct eth_pdata *plat = dev_get_platdata(dev);
413 struct phy_device *phydev;
414 int mask = 0xffffffff;
415
416 phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
417 if (!phydev) {
418 printf("pch_gbe: cannot find the phy\n");
419 return -1;
420 }
421
422 phy_connect_dev(phydev, dev);
423
424 phydev->supported &= PHY_GBIT_FEATURES;
425 phydev->advertising = phydev->supported;
426
427 priv->phydev = phydev;
428 phy_config(phydev);
429
430 return 0;
431 }
432
pch_gbe_probe(struct udevice * dev)433 static int pch_gbe_probe(struct udevice *dev)
434 {
435 struct pch_gbe_priv *priv;
436 struct eth_pdata *plat = dev_get_platdata(dev);
437 void *iobase;
438 int err;
439
440 /*
441 * The priv structure contains the descriptors and frame buffers which
442 * need a strict buswidth alignment (64 bytes). This is guaranteed by
443 * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
444 */
445 priv = dev_get_priv(dev);
446
447 priv->dev = dev;
448
449 iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
450
451 plat->iobase = (ulong)iobase;
452 priv->mac_regs = (struct pch_gbe_regs *)iobase;
453
454 /* Read MAC address from SROM and initialize dev->enetaddr with it */
455 pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
456
457 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
458 pch_gbe_mdio_init(dev->name, priv->mac_regs);
459 priv->bus = miiphy_get_dev_by_name(dev->name);
460
461 err = pch_gbe_reset(dev);
462 if (err)
463 return err;
464
465 return pch_gbe_phy_init(dev);
466 }
467
pch_gbe_remove(struct udevice * dev)468 static int pch_gbe_remove(struct udevice *dev)
469 {
470 struct pch_gbe_priv *priv = dev_get_priv(dev);
471
472 free(priv->phydev);
473 mdio_unregister(priv->bus);
474 mdio_free(priv->bus);
475
476 return 0;
477 }
478
479 static const struct eth_ops pch_gbe_ops = {
480 .start = pch_gbe_start,
481 .send = pch_gbe_send,
482 .recv = pch_gbe_recv,
483 .free_pkt = pch_gbe_free_pkt,
484 .stop = pch_gbe_stop,
485 };
486
487 static const struct udevice_id pch_gbe_ids[] = {
488 { .compatible = "intel,pch-gbe" },
489 { }
490 };
491
492 U_BOOT_DRIVER(eth_pch_gbe) = {
493 .name = "pch_gbe",
494 .id = UCLASS_ETH,
495 .of_match = pch_gbe_ids,
496 .probe = pch_gbe_probe,
497 .remove = pch_gbe_remove,
498 .ops = &pch_gbe_ops,
499 .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
500 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
501 .flags = DM_FLAG_ALLOC_PRIV_DMA,
502 };
503
504 U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);
505