1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
4 *
5 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
6 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 */
9
10 #include <netdev.h>
11 #include <asm/types.h>
12
13 #define SHETHER_NAME "sh_eth"
14
15 #if defined(CONFIG_SH)
16 /* Malloc returns addresses in the P1 area (cacheable). However we need to
17 use area P2 (non-cacheable) */
18 #define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
19
20 /* The ethernet controller needs to use physical addresses */
21 #if defined(CONFIG_SH_32BIT)
22 #define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
23 #else
24 #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
25 #endif
26 #elif defined(CONFIG_ARM)
27 #ifndef inl
28 #define inl readl
29 #define outl writel
30 #endif
31 #define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
32 #define ADDR_TO_P2(addr) (addr)
33 #endif /* defined(CONFIG_SH) */
34
35 /* base padding size is 16 */
36 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
37 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
38 #endif
39
40 /* Number of supported ports */
41 #define MAX_PORT_NUM 2
42
43 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
44 buffers must be a multiple of 32 bytes */
45 #define MAX_BUF_SIZE (48 * 32)
46
47 /* The number of tx descriptors must be large enough to point to 5 or more
48 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
49 We use one descriptor per frame */
50 #define NUM_TX_DESC 8
51
52 /* The size of the tx descriptor is determined by how much padding is used.
53 4, 20, or 52 bytes of padding can be used */
54 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
55
56 /* Tx descriptor. We always use 3 bytes of padding */
57 struct tx_desc_s {
58 volatile u32 td0;
59 u32 td1;
60 u32 td2; /* Buffer start */
61 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
62 };
63
64 /* There is no limitation in the number of rx descriptors */
65 #define NUM_RX_DESC 8
66
67 /* The size of the rx descriptor is determined by how much padding is used.
68 4, 20, or 52 bytes of padding can be used */
69 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
70 /* aligned cache line size */
71 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
72
73 /* Rx descriptor. We always use 4 bytes of padding */
74 struct rx_desc_s {
75 volatile u32 rd0;
76 volatile u32 rd1;
77 u32 rd2; /* Buffer start */
78 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
79 };
80
81 struct sh_eth_info {
82 struct tx_desc_s *tx_desc_alloc;
83 struct tx_desc_s *tx_desc_base;
84 struct tx_desc_s *tx_desc_cur;
85 struct rx_desc_s *rx_desc_alloc;
86 struct rx_desc_s *rx_desc_base;
87 struct rx_desc_s *rx_desc_cur;
88 u8 *rx_buf_alloc;
89 u8 *rx_buf_base;
90 u8 mac_addr[6];
91 u8 phy_addr;
92 struct eth_device *dev;
93 struct phy_device *phydev;
94 void __iomem *iobase;
95 };
96
97 struct sh_eth_dev {
98 int port;
99 struct sh_eth_info port_info[MAX_PORT_NUM];
100 };
101
102 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
103 enum {
104 /* E-DMAC registers */
105 EDSR = 0,
106 EDMR,
107 EDTRR,
108 EDRRR,
109 EESR,
110 EESIPR,
111 TDLAR,
112 TDFAR,
113 TDFXR,
114 TDFFR,
115 RDLAR,
116 RDFAR,
117 RDFXR,
118 RDFFR,
119 TRSCER,
120 RMFCR,
121 TFTR,
122 FDR,
123 RMCR,
124 EDOCR,
125 TFUCR,
126 RFOCR,
127 FCFTR,
128 RPADIR,
129 TRIMD,
130 RBWAR,
131 TBRAR,
132
133 /* Ether registers */
134 ECMR,
135 ECSR,
136 ECSIPR,
137 PIR,
138 PSR,
139 RDMLR,
140 PIPR,
141 RFLR,
142 IPGR,
143 APR,
144 MPR,
145 PFTCR,
146 PFRCR,
147 RFCR,
148 RFCF,
149 TPAUSER,
150 TPAUSECR,
151 BCFR,
152 BCFRR,
153 GECMR,
154 BCULR,
155 MAHR,
156 MALR,
157 TROCR,
158 CDCR,
159 LCCR,
160 CNDCR,
161 CEFCR,
162 FRECR,
163 TSFRCR,
164 TLFRCR,
165 CERCR,
166 CEECR,
167 RMIIMR, /* R8A7790 */
168 MAFCR,
169 RTRATE,
170 CSMR,
171 RMII_MII,
172
173 /* This value must be written at last. */
174 SH_ETH_MAX_REGISTER_OFFSET,
175 };
176
177 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
178 [EDSR] = 0x0000,
179 [EDMR] = 0x0400,
180 [EDTRR] = 0x0408,
181 [EDRRR] = 0x0410,
182 [EESR] = 0x0428,
183 [EESIPR] = 0x0430,
184 [TDLAR] = 0x0010,
185 [TDFAR] = 0x0014,
186 [TDFXR] = 0x0018,
187 [TDFFR] = 0x001c,
188 [RDLAR] = 0x0030,
189 [RDFAR] = 0x0034,
190 [RDFXR] = 0x0038,
191 [RDFFR] = 0x003c,
192 [TRSCER] = 0x0438,
193 [RMFCR] = 0x0440,
194 [TFTR] = 0x0448,
195 [FDR] = 0x0450,
196 [RMCR] = 0x0458,
197 [RPADIR] = 0x0460,
198 [FCFTR] = 0x0468,
199 [CSMR] = 0x04E4,
200
201 [ECMR] = 0x0500,
202 [ECSR] = 0x0510,
203 [ECSIPR] = 0x0518,
204 [PIR] = 0x0520,
205 [PSR] = 0x0528,
206 [PIPR] = 0x052c,
207 [RFLR] = 0x0508,
208 [APR] = 0x0554,
209 [MPR] = 0x0558,
210 [PFTCR] = 0x055c,
211 [PFRCR] = 0x0560,
212 [TPAUSER] = 0x0564,
213 [GECMR] = 0x05b0,
214 [BCULR] = 0x05b4,
215 [MAHR] = 0x05c0,
216 [MALR] = 0x05c8,
217 [TROCR] = 0x0700,
218 [CDCR] = 0x0708,
219 [LCCR] = 0x0710,
220 [CEFCR] = 0x0740,
221 [FRECR] = 0x0748,
222 [TSFRCR] = 0x0750,
223 [TLFRCR] = 0x0758,
224 [RFCR] = 0x0760,
225 [CERCR] = 0x0768,
226 [CEECR] = 0x0770,
227 [MAFCR] = 0x0778,
228 [RMII_MII] = 0x0790,
229 };
230
231 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
232 [EDSR] = 0x0000,
233 [EDMR] = 0x0400,
234 [EDTRR] = 0x0408,
235 [EDRRR] = 0x0410,
236 [EESR] = 0x0428,
237 [EESIPR] = 0x0430,
238 [TDLAR] = 0x0010,
239 [TDFAR] = 0x0014,
240 [TDFXR] = 0x0018,
241 [TDFFR] = 0x001c,
242 [RDLAR] = 0x0030,
243 [RDFAR] = 0x0034,
244 [RDFXR] = 0x0038,
245 [RDFFR] = 0x003c,
246 [TRSCER] = 0x0438,
247 [RMFCR] = 0x0440,
248 [TFTR] = 0x0448,
249 [FDR] = 0x0450,
250 [RMCR] = 0x0458,
251 [RPADIR] = 0x0460,
252 [FCFTR] = 0x0468,
253 [CSMR] = 0x04E4,
254
255 [ECMR] = 0x0500,
256 [ECSR] = 0x0510,
257 [ECSIPR] = 0x0518,
258 [PIR] = 0x0520,
259 [PSR] = 0x0528,
260 [PIPR] = 0x052c,
261 [RFLR] = 0x0508,
262 [APR] = 0x0554,
263 [MPR] = 0x0558,
264 [PFTCR] = 0x055c,
265 [PFRCR] = 0x0560,
266 [TPAUSER] = 0x0564,
267 [GECMR] = 0x05b0,
268 [BCULR] = 0x05b4,
269 [MAHR] = 0x05c0,
270 [MALR] = 0x05c8,
271 [TROCR] = 0x0700,
272 [CDCR] = 0x0708,
273 [LCCR] = 0x0710,
274 [CEFCR] = 0x0740,
275 [FRECR] = 0x0748,
276 [TSFRCR] = 0x0750,
277 [TLFRCR] = 0x0758,
278 [RFCR] = 0x0760,
279 [CERCR] = 0x0768,
280 [CEECR] = 0x0770,
281 [MAFCR] = 0x0778,
282 [RMII_MII] = 0x0790,
283 };
284
285 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
286 [ECMR] = 0x0100,
287 [RFLR] = 0x0108,
288 [ECSR] = 0x0110,
289 [ECSIPR] = 0x0118,
290 [PIR] = 0x0120,
291 [PSR] = 0x0128,
292 [RDMLR] = 0x0140,
293 [IPGR] = 0x0150,
294 [APR] = 0x0154,
295 [MPR] = 0x0158,
296 [TPAUSER] = 0x0164,
297 [RFCF] = 0x0160,
298 [TPAUSECR] = 0x0168,
299 [BCFRR] = 0x016c,
300 [MAHR] = 0x01c0,
301 [MALR] = 0x01c8,
302 [TROCR] = 0x01d0,
303 [CDCR] = 0x01d4,
304 [LCCR] = 0x01d8,
305 [CNDCR] = 0x01dc,
306 [CEFCR] = 0x01e4,
307 [FRECR] = 0x01e8,
308 [TSFRCR] = 0x01ec,
309 [TLFRCR] = 0x01f0,
310 [RFCR] = 0x01f4,
311 [MAFCR] = 0x01f8,
312 [RTRATE] = 0x01fc,
313
314 [EDMR] = 0x0000,
315 [EDTRR] = 0x0008,
316 [EDRRR] = 0x0010,
317 [TDLAR] = 0x0018,
318 [RDLAR] = 0x0020,
319 [EESR] = 0x0028,
320 [EESIPR] = 0x0030,
321 [TRSCER] = 0x0038,
322 [RMFCR] = 0x0040,
323 [TFTR] = 0x0048,
324 [FDR] = 0x0050,
325 [RMCR] = 0x0058,
326 [TFUCR] = 0x0064,
327 [RFOCR] = 0x0068,
328 [RMIIMR] = 0x006C,
329 [FCFTR] = 0x0070,
330 [RPADIR] = 0x0078,
331 [TRIMD] = 0x007c,
332 [RBWAR] = 0x00c8,
333 [RDFAR] = 0x00cc,
334 [TBRAR] = 0x00d4,
335 [TDFAR] = 0x00d8,
336 };
337
338 /* Register Address */
339 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
340 #define SH_ETH_TYPE_GETHER
341 #define BASE_IO_ADDR 0xfee00000
342 #elif defined(CONFIG_CPU_SH7757) || \
343 defined(CONFIG_CPU_SH7752) || \
344 defined(CONFIG_CPU_SH7753)
345 #if defined(CONFIG_SH_ETHER_USE_GETHER)
346 #define SH_ETH_TYPE_GETHER
347 #define BASE_IO_ADDR 0xfee00000
348 #else
349 #define SH_ETH_TYPE_ETHER
350 #define BASE_IO_ADDR 0xfef00000
351 #endif
352 #elif defined(CONFIG_R8A7740)
353 #define SH_ETH_TYPE_GETHER
354 #define BASE_IO_ADDR 0xE9A00000
355 #elif defined(CONFIG_RCAR_GEN2)
356 #define SH_ETH_TYPE_ETHER
357 #define BASE_IO_ADDR 0xEE700200
358 #elif defined(CONFIG_R7S72100)
359 #define SH_ETH_TYPE_RZ
360 #define BASE_IO_ADDR 0xE8203000
361 #elif defined(CONFIG_R8A77980)
362 #define SH_ETH_TYPE_GETHER
363 #define BASE_IO_ADDR 0xE7400000
364 #endif
365
366 /*
367 * Register's bits
368 * Copy from Linux driver source code
369 */
370 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
371 /* EDSR */
372 enum EDSR_BIT {
373 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
374 };
375 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
376 #endif
377
378 /* EDMR */
379 enum DMAC_M_BIT {
380 EDMR_NBST = 0x80, /* DMA transfer burst mode */
381 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
382 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
383 EDMR_SRST = 0x03, /* Receive/Send reset */
384 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
385 EDMR_EL = 0x40, /* Litte endian */
386 #elif defined(SH_ETH_TYPE_ETHER)
387 EDMR_SRST = 0x01,
388 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
389 EDMR_EL = 0x40, /* Litte endian */
390 #else
391 EDMR_SRST = 0x01,
392 #endif
393 };
394
395 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
396 # define EMDR_DESC EDMR_DL1
397 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
398 # define EMDR_DESC EDMR_DL0
399 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
400 # define EMDR_DESC 0
401 #endif
402
403 /* RFLR */
404 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
405
406 /* EDTRR */
407 enum DMAC_T_BIT {
408 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
409 EDTRR_TRNS = 0x03,
410 #else
411 EDTRR_TRNS = 0x01,
412 #endif
413 };
414
415 /* GECMR */
416 enum GECMR_BIT {
417 #if defined(CONFIG_CPU_SH7757) || \
418 defined(CONFIG_CPU_SH7752) || \
419 defined(CONFIG_CPU_SH7753)
420 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
421 #else
422 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
423 #endif
424 };
425
426 /* EDRRR*/
427 enum EDRRR_R_BIT {
428 EDRRR_R = 0x01,
429 };
430
431 /* TPAUSER */
432 enum TPAUSER_BIT {
433 TPAUSER_TPAUSE = 0x0000ffff,
434 TPAUSER_UNLIMITED = 0,
435 };
436
437 /* BCFR */
438 enum BCFR_BIT {
439 BCFR_RPAUSE = 0x0000ffff,
440 BCFR_UNLIMITED = 0,
441 };
442
443 /* PIR */
444 enum PIR_BIT {
445 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
446 };
447
448 /* PSR */
449 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
450
451 /* EESR */
452 enum EESR_BIT {
453 #if defined(SH_ETH_TYPE_ETHER)
454 EESR_TWB = 0x40000000,
455 #else
456 EESR_TWB = 0xC0000000,
457 EESR_TC1 = 0x20000000,
458 EESR_TUC = 0x10000000,
459 EESR_ROC = 0x80000000,
460 #endif
461 EESR_TABT = 0x04000000,
462 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
463 #if defined(SH_ETH_TYPE_ETHER)
464 EESR_ADE = 0x00800000,
465 #endif
466 EESR_ECI = 0x00400000,
467 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
468 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
469 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
470 #if defined(SH_ETH_TYPE_ETHER)
471 EESR_CND = 0x00000800,
472 #endif
473 EESR_DLC = 0x00000400,
474 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
475 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
476 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
477 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
478 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
479 };
480
481
482 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
483 # define TX_CHECK (EESR_TC1 | EESR_FTC)
484 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
485 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
486 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
487
488 #else
489 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
490 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
491 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
492 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
493 #endif
494
495 /* EESIPR */
496 enum DMAC_IM_BIT {
497 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
498 DMAC_M_RABT = 0x02000000,
499 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
500 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
501 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
502 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
503 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
504 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
505 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
506 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
507 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
508 DMAC_M_RINT1 = 0x00000001,
509 };
510
511 /* Receive descriptor bit */
512 enum RD_STS_BIT {
513 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
514 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
515 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
516 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
517 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
518 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
519 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
520 RD_RFS1 = 0x00000001,
521 };
522 #define RDF1ST RD_RFP1
523 #define RDFEND RD_RFP0
524 #define RD_RFP (RD_RFP1|RD_RFP0)
525
526 /* RDFFR*/
527 enum RDFFR_BIT {
528 RDFFR_RDLF = 0x01,
529 };
530
531 /* FCFTR */
532 enum FCFTR_BIT {
533 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
534 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
535 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
536 };
537 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
538 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
539
540 /* Transfer descriptor bit */
541 enum TD_STS_BIT {
542 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
543 defined(SH_ETH_TYPE_RZ)
544 TD_TACT = 0x80000000,
545 #else
546 TD_TACT = 0x7fffffff,
547 #endif
548 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
549 TD_TFP0 = 0x10000000,
550 };
551 #define TDF1ST TD_TFP1
552 #define TDFEND TD_TFP0
553 #define TD_TFP (TD_TFP1|TD_TFP0)
554
555 /* RMCR */
556 enum RECV_RST_BIT { RMCR_RST = 0x01, };
557 /* ECMR */
558 enum FELIC_MODE_BIT {
559 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
560 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
561 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
562 #endif
563 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
564 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
565 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
566 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
567 ECMR_PRM = 0x00000001,
568 #ifdef CONFIG_CPU_SH7724
569 ECMR_RTM = 0x00000010,
570 #elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
571 ECMR_RTM = 0x00000004,
572 #endif
573
574 };
575
576 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
577 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
578 ECMR_RXF | ECMR_TXF | ECMR_MCT)
579 #elif defined(SH_ETH_TYPE_ETHER)
580 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
581 #else
582 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
583 #endif
584
585 /* ECSR */
586 enum ECSR_STATUS_BIT {
587 #if defined(SH_ETH_TYPE_ETHER)
588 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
589 #endif
590 ECSR_LCHNG = 0x04,
591 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
592 };
593
594 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
595 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
596 #else
597 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
598 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
599 #endif
600
601 /* ECSIPR */
602 enum ECSIPR_STATUS_MASK_BIT {
603 #if defined(SH_ETH_TYPE_ETHER)
604 ECSIPR_BRCRXIP = 0x20,
605 ECSIPR_PSRTOIP = 0x10,
606 #elif defined(SH_ETY_TYPE_GETHER)
607 ECSIPR_PSRTOIP = 0x10,
608 ECSIPR_PHYIP = 0x08,
609 #endif
610 ECSIPR_LCHNGIP = 0x04,
611 ECSIPR_MPDIP = 0x02,
612 ECSIPR_ICDIP = 0x01,
613 };
614
615 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
616 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
617 #else
618 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
619 ECSIPR_ICDIP | ECSIPR_MPDIP)
620 #endif
621
622 /* APR */
623 enum APR_BIT {
624 APR_AP = 0x00000004,
625 };
626
627 /* MPR */
628 enum MPR_BIT {
629 MPR_MP = 0x00000006,
630 };
631
632 /* TRSCER */
633 enum DESC_I_BIT {
634 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
635 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
636 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
637 DESC_I_RINT1 = 0x0001,
638 };
639
640 /* RPADIR */
641 enum RPADIR_BIT {
642 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
643 RPADIR_PADR = 0x0003f,
644 };
645
646 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
647 # define RPADIR_INIT (0x00)
648 #else
649 # define RPADIR_INIT (RPADIR_PADS1)
650 #endif
651
652 /* FDR */
653 enum FIFO_SIZE_BIT {
654 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
655 };
656
sh_eth_reg_addr(struct sh_eth_info * port,int enum_index)657 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
658 int enum_index)
659 {
660 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
661 const u16 *reg_offset = sh_eth_offset_gigabit;
662 #elif defined(SH_ETH_TYPE_ETHER)
663 const u16 *reg_offset = sh_eth_offset_fast_sh4;
664 #elif defined(SH_ETH_TYPE_RZ)
665 const u16 *reg_offset = sh_eth_offset_rz;
666 #else
667 #error
668 #endif
669 return (unsigned long)port->iobase + reg_offset[enum_index];
670 }
671
sh_eth_write(struct sh_eth_info * port,unsigned long data,int enum_index)672 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
673 int enum_index)
674 {
675 outl(data, sh_eth_reg_addr(port, enum_index));
676 }
677
sh_eth_read(struct sh_eth_info * port,int enum_index)678 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
679 int enum_index)
680 {
681 return inl(sh_eth_reg_addr(port, enum_index));
682 }
683