1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <net.h>
13 #include <malloc.h>
14 #include <asm/io.h>
15 #include <phy.h>
16 #include <miiphy.h>
17 #include <wait_bit.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* Link setup */
22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
26
27 /* Interrupt Status/Enable/Mask Registers bit definitions */
28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
30
31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
33
34 /* Transmitter Configuration (TC) Register bit definitions */
35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
36
37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
38
39 /* MDIO Management Configuration (MC) Register bit definitions */
40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
41
42 /* MDIO Management Control Register (MCR) Register bit definitions */
43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
51
52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
53
54 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
55
56 /* DMA macros */
57 /* Bitmasks of XAXIDMA_CR_OFFSET register */
58 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
59 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
60
61 /* Bitmasks of XAXIDMA_SR_OFFSET register */
62 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
63
64 /* Bitmask for interrupts */
65 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
66 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
67 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
68
69 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
70 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
71 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
72
73 #define DMAALIGN 128
74
75 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
76
77 /* Reflect dma offsets */
78 struct axidma_reg {
79 u32 control; /* DMACR */
80 u32 status; /* DMASR */
81 u32 current; /* CURDESC low 32 bit */
82 u32 current_hi; /* CURDESC high 32 bit */
83 u32 tail; /* TAILDESC low 32 bit */
84 u32 tail_hi; /* TAILDESC high 32 bit */
85 };
86
87 /* Private driver structures */
88 struct axidma_priv {
89 struct axidma_reg *dmatx;
90 struct axidma_reg *dmarx;
91 int phyaddr;
92 struct axi_regs *iobase;
93 phy_interface_t interface;
94 struct phy_device *phydev;
95 struct mii_dev *bus;
96 u8 eth_hasnobuf;
97 int phy_of_handle;
98 };
99
100 /* BD descriptors */
101 struct axidma_bd {
102 u32 next; /* Next descriptor pointer */
103 u32 reserved1;
104 u32 phys; /* Buffer address */
105 u32 reserved2;
106 u32 reserved3;
107 u32 reserved4;
108 u32 cntrl; /* Control */
109 u32 status; /* Status */
110 u32 app0;
111 u32 app1; /* TX start << 16 | insert */
112 u32 app2; /* TX csum seed */
113 u32 app3;
114 u32 app4;
115 u32 sw_id_offset;
116 u32 reserved5;
117 u32 reserved6;
118 };
119
120 /* Static BDs - driver uses only one BD */
121 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
122 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
123
124 struct axi_regs {
125 u32 reserved[3];
126 u32 is; /* 0xC: Interrupt status */
127 u32 reserved2;
128 u32 ie; /* 0x14: Interrupt enable */
129 u32 reserved3[251];
130 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
131 u32 tc; /* 0x408: Tx Configuration */
132 u32 reserved4;
133 u32 emmc; /* 0x410: EMAC mode configuration */
134 u32 reserved5[59];
135 u32 mdio_mc; /* 0x500: MII Management Config */
136 u32 mdio_mcr; /* 0x504: MII Management Control */
137 u32 mdio_mwd; /* 0x508: MII Management Write Data */
138 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
139 u32 reserved6[124];
140 u32 uaw0; /* 0x700: Unicast address word 0 */
141 u32 uaw1; /* 0x704: Unicast address word 1 */
142 };
143
144 /* Use MII register 1 (MII status register) to detect PHY */
145 #define PHY_DETECT_REG 1
146
147 /*
148 * Mask used to verify certain PHY features (or register contents)
149 * in the register above:
150 * 0x1000: 10Mbps full duplex support
151 * 0x0800: 10Mbps half duplex support
152 * 0x0008: Auto-negotiation support
153 */
154 #define PHY_DETECT_MASK 0x1808
155
mdio_wait(struct axi_regs * regs)156 static inline int mdio_wait(struct axi_regs *regs)
157 {
158 u32 timeout = 200;
159
160 /* Wait till MDIO interface is ready to accept a new transaction. */
161 while (timeout && (!(readl(®s->mdio_mcr)
162 & XAE_MDIO_MCR_READY_MASK))) {
163 timeout--;
164 udelay(1);
165 }
166 if (!timeout) {
167 printf("%s: Timeout\n", __func__);
168 return 1;
169 }
170 return 0;
171 }
172
173 /**
174 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
175 * @bd: pointer to BD descriptor structure
176 * @desc: Address offset of DMA descriptors
177 *
178 * This function writes the value into the corresponding Axi DMA register.
179 */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)180 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
181 {
182 #if defined(CONFIG_PHYS_64BIT)
183 writeq(bd, desc);
184 #else
185 writel((u32)bd, desc);
186 #endif
187 }
188
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)189 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
190 u16 *val)
191 {
192 struct axi_regs *regs = priv->iobase;
193 u32 mdioctrlreg = 0;
194
195 if (mdio_wait(regs))
196 return 1;
197
198 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
199 XAE_MDIO_MCR_PHYAD_MASK) |
200 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
201 & XAE_MDIO_MCR_REGAD_MASK) |
202 XAE_MDIO_MCR_INITIATE_MASK |
203 XAE_MDIO_MCR_OP_READ_MASK;
204
205 writel(mdioctrlreg, ®s->mdio_mcr);
206
207 if (mdio_wait(regs))
208 return 1;
209
210 /* Read data */
211 *val = readl(®s->mdio_mrd);
212 return 0;
213 }
214
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)215 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
216 u32 data)
217 {
218 struct axi_regs *regs = priv->iobase;
219 u32 mdioctrlreg = 0;
220
221 if (mdio_wait(regs))
222 return 1;
223
224 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
225 XAE_MDIO_MCR_PHYAD_MASK) |
226 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
227 & XAE_MDIO_MCR_REGAD_MASK) |
228 XAE_MDIO_MCR_INITIATE_MASK |
229 XAE_MDIO_MCR_OP_WRITE_MASK;
230
231 /* Write data */
232 writel(data, ®s->mdio_mwd);
233
234 writel(mdioctrlreg, ®s->mdio_mcr);
235
236 if (mdio_wait(regs))
237 return 1;
238
239 return 0;
240 }
241
axiemac_phy_init(struct udevice * dev)242 static int axiemac_phy_init(struct udevice *dev)
243 {
244 u16 phyreg;
245 u32 i, ret;
246 struct axidma_priv *priv = dev_get_priv(dev);
247 struct axi_regs *regs = priv->iobase;
248 struct phy_device *phydev;
249
250 u32 supported = SUPPORTED_10baseT_Half |
251 SUPPORTED_10baseT_Full |
252 SUPPORTED_100baseT_Half |
253 SUPPORTED_100baseT_Full |
254 SUPPORTED_1000baseT_Half |
255 SUPPORTED_1000baseT_Full;
256
257 /* Set default MDIO divisor */
258 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
259
260 if (priv->phyaddr == -1) {
261 /* Detect the PHY address */
262 for (i = 31; i >= 0; i--) {
263 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
264 if (!ret && (phyreg != 0xFFFF) &&
265 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
266 /* Found a valid PHY address */
267 priv->phyaddr = i;
268 debug("axiemac: Found valid phy address, %x\n",
269 i);
270 break;
271 }
272 }
273 }
274
275 /* Interface - look at tsec */
276 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
277
278 phydev->supported &= supported;
279 phydev->advertising = phydev->supported;
280 priv->phydev = phydev;
281 if (priv->phy_of_handle)
282 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
283 phy_config(phydev);
284
285 return 0;
286 }
287
288 /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)289 static int setup_phy(struct udevice *dev)
290 {
291 u16 temp;
292 u32 speed, emmc_reg, ret;
293 struct axidma_priv *priv = dev_get_priv(dev);
294 struct axi_regs *regs = priv->iobase;
295 struct phy_device *phydev = priv->phydev;
296
297 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
298 /*
299 * In SGMII cases the isolate bit might set
300 * after DMA and ethernet resets and hence
301 * check and clear if set.
302 */
303 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
304 if (ret)
305 return 0;
306 if (temp & BMCR_ISOLATE) {
307 temp &= ~BMCR_ISOLATE;
308 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
309 if (ret)
310 return 0;
311 }
312 }
313
314 if (phy_startup(phydev)) {
315 printf("axiemac: could not initialize PHY %s\n",
316 phydev->dev->name);
317 return 0;
318 }
319 if (!phydev->link) {
320 printf("%s: No link.\n", phydev->dev->name);
321 return 0;
322 }
323
324 switch (phydev->speed) {
325 case 1000:
326 speed = XAE_EMMC_LINKSPD_1000;
327 break;
328 case 100:
329 speed = XAE_EMMC_LINKSPD_100;
330 break;
331 case 10:
332 speed = XAE_EMMC_LINKSPD_10;
333 break;
334 default:
335 return 0;
336 }
337
338 /* Setup the emac for the phy speed */
339 emmc_reg = readl(®s->emmc);
340 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
341 emmc_reg |= speed;
342
343 /* Write new speed setting out to Axi Ethernet */
344 writel(emmc_reg, ®s->emmc);
345
346 /*
347 * Setting the operating speed of the MAC needs a delay. There
348 * doesn't seem to be register to poll, so please consider this
349 * during your application design.
350 */
351 udelay(1);
352
353 return 1;
354 }
355
356 /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)357 static void axiemac_stop(struct udevice *dev)
358 {
359 struct axidma_priv *priv = dev_get_priv(dev);
360 u32 temp;
361
362 /* Stop the hardware */
363 temp = readl(&priv->dmatx->control);
364 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
365 writel(temp, &priv->dmatx->control);
366
367 temp = readl(&priv->dmarx->control);
368 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
369 writel(temp, &priv->dmarx->control);
370
371 debug("axiemac: Halted\n");
372 }
373
axi_ethernet_init(struct axidma_priv * priv)374 static int axi_ethernet_init(struct axidma_priv *priv)
375 {
376 struct axi_regs *regs = priv->iobase;
377 int err;
378
379 /*
380 * Check the status of the MgtRdy bit in the interrupt status
381 * registers. This must be done to allow the MGT clock to become stable
382 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
383 * will be valid until this bit is valid.
384 * The bit is always a 1 for all other PHY interfaces.
385 * Interrupt status and enable registers are not available in non
386 * processor mode and hence bypass in this mode
387 */
388 if (!priv->eth_hasnobuf) {
389 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
390 true, 200, false);
391 if (err) {
392 printf("%s: Timeout\n", __func__);
393 return 1;
394 }
395
396 /*
397 * Stop the device and reset HW
398 * Disable interrupts
399 */
400 writel(0, ®s->ie);
401 }
402
403 /* Disable the receiver */
404 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
405
406 /*
407 * Stopping the receiver in mid-packet causes a dropped packet
408 * indication from HW. Clear it.
409 */
410 if (!priv->eth_hasnobuf) {
411 /* Set the interrupt status register to clear the interrupt */
412 writel(XAE_INT_RXRJECT_MASK, ®s->is);
413 }
414
415 /* Setup HW */
416 /* Set default MDIO divisor */
417 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
418
419 debug("axiemac: InitHw done\n");
420 return 0;
421 }
422
axiemac_write_hwaddr(struct udevice * dev)423 static int axiemac_write_hwaddr(struct udevice *dev)
424 {
425 struct eth_pdata *pdata = dev_get_platdata(dev);
426 struct axidma_priv *priv = dev_get_priv(dev);
427 struct axi_regs *regs = priv->iobase;
428
429 /* Set the MAC address */
430 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
431 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
432 writel(val, ®s->uaw0);
433
434 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
435 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
436 writel(val, ®s->uaw1);
437 return 0;
438 }
439
440 /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)441 static void axi_dma_init(struct axidma_priv *priv)
442 {
443 u32 timeout = 500;
444
445 /* Reset the engine so the hardware starts from a known state */
446 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
447 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
448
449 /* At the initialization time, hardware should finish reset quickly */
450 while (timeout--) {
451 /* Check transmit/receive channel */
452 /* Reset is done when the reset bit is low */
453 if (!((readl(&priv->dmatx->control) |
454 readl(&priv->dmarx->control))
455 & XAXIDMA_CR_RESET_MASK)) {
456 break;
457 }
458 }
459 if (!timeout)
460 printf("%s: Timeout\n", __func__);
461 }
462
axiemac_start(struct udevice * dev)463 static int axiemac_start(struct udevice *dev)
464 {
465 struct axidma_priv *priv = dev_get_priv(dev);
466 struct axi_regs *regs = priv->iobase;
467 u32 temp;
468
469 debug("axiemac: Init started\n");
470 /*
471 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
472 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
473 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
474 * would ensure a reset of AxiEthernet.
475 */
476 axi_dma_init(priv);
477
478 /* Initialize AxiEthernet hardware. */
479 if (axi_ethernet_init(priv))
480 return -1;
481
482 /* Disable all RX interrupts before RxBD space setup */
483 temp = readl(&priv->dmarx->control);
484 temp &= ~XAXIDMA_IRQ_ALL_MASK;
485 writel(temp, &priv->dmarx->control);
486
487 /* Start DMA RX channel. Now it's ready to receive data.*/
488 axienet_dma_write(&rx_bd, &priv->dmarx->current);
489
490 /* Setup the BD. */
491 memset(&rx_bd, 0, sizeof(rx_bd));
492 rx_bd.next = (u32)&rx_bd;
493 rx_bd.phys = (u32)&rxframe;
494 rx_bd.cntrl = sizeof(rxframe);
495 /* Flush the last BD so DMA core could see the updates */
496 flush_cache((u32)&rx_bd, sizeof(rx_bd));
497
498 /* It is necessary to flush rxframe because if you don't do it
499 * then cache can contain uninitialized data */
500 flush_cache((u32)&rxframe, sizeof(rxframe));
501
502 /* Start the hardware */
503 temp = readl(&priv->dmarx->control);
504 temp |= XAXIDMA_CR_RUNSTOP_MASK;
505 writel(temp, &priv->dmarx->control);
506
507 /* Rx BD is ready - start */
508 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
509
510 /* Enable TX */
511 writel(XAE_TC_TX_MASK, ®s->tc);
512 /* Enable RX */
513 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
514
515 /* PHY setup */
516 if (!setup_phy(dev)) {
517 axiemac_stop(dev);
518 return -1;
519 }
520
521 debug("axiemac: Init complete\n");
522 return 0;
523 }
524
axiemac_send(struct udevice * dev,void * ptr,int len)525 static int axiemac_send(struct udevice *dev, void *ptr, int len)
526 {
527 struct axidma_priv *priv = dev_get_priv(dev);
528 u32 timeout;
529
530 if (len > PKTSIZE_ALIGN)
531 len = PKTSIZE_ALIGN;
532
533 /* Flush packet to main memory to be trasfered by DMA */
534 flush_cache((u32)ptr, len);
535
536 /* Setup Tx BD */
537 memset(&tx_bd, 0, sizeof(tx_bd));
538 /* At the end of the ring, link the last BD back to the top */
539 tx_bd.next = (u32)&tx_bd;
540 tx_bd.phys = (u32)ptr;
541 /* Save len */
542 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
543 XAXIDMA_BD_CTRL_TXEOF_MASK;
544
545 /* Flush the last BD so DMA core could see the updates */
546 flush_cache((u32)&tx_bd, sizeof(tx_bd));
547
548 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
549 u32 temp;
550 axienet_dma_write(&tx_bd, &priv->dmatx->current);
551 /* Start the hardware */
552 temp = readl(&priv->dmatx->control);
553 temp |= XAXIDMA_CR_RUNSTOP_MASK;
554 writel(temp, &priv->dmatx->control);
555 }
556
557 /* Start transfer */
558 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
559
560 /* Wait for transmission to complete */
561 debug("axiemac: Waiting for tx to be done\n");
562 timeout = 200;
563 while (timeout && (!(readl(&priv->dmatx->status) &
564 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
565 timeout--;
566 udelay(1);
567 }
568 if (!timeout) {
569 printf("%s: Timeout\n", __func__);
570 return 1;
571 }
572
573 debug("axiemac: Sending complete\n");
574 return 0;
575 }
576
isrxready(struct axidma_priv * priv)577 static int isrxready(struct axidma_priv *priv)
578 {
579 u32 status;
580
581 /* Read pending interrupts */
582 status = readl(&priv->dmarx->status);
583
584 /* Acknowledge pending interrupts */
585 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
586
587 /*
588 * If Reception done interrupt is asserted, call RX call back function
589 * to handle the processed BDs and then raise the according flag.
590 */
591 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
592 return 1;
593
594 return 0;
595 }
596
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)597 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
598 {
599 u32 length;
600 struct axidma_priv *priv = dev_get_priv(dev);
601 u32 temp;
602
603 /* Wait for an incoming packet */
604 if (!isrxready(priv))
605 return -1;
606
607 debug("axiemac: RX data ready\n");
608
609 /* Disable IRQ for a moment till packet is handled */
610 temp = readl(&priv->dmarx->control);
611 temp &= ~XAXIDMA_IRQ_ALL_MASK;
612 writel(temp, &priv->dmarx->control);
613 if (!priv->eth_hasnobuf)
614 length = rx_bd.app4 & 0xFFFF; /* max length mask */
615 else
616 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
617
618 #ifdef DEBUG
619 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
620 #endif
621
622 *packetp = rxframe;
623 return length;
624 }
625
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)626 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
627 {
628 struct axidma_priv *priv = dev_get_priv(dev);
629
630 #ifdef DEBUG
631 /* It is useful to clear buffer to be sure that it is consistent */
632 memset(rxframe, 0, sizeof(rxframe));
633 #endif
634 /* Setup RxBD */
635 /* Clear the whole buffer and setup it again - all flags are cleared */
636 memset(&rx_bd, 0, sizeof(rx_bd));
637 rx_bd.next = (u32)&rx_bd;
638 rx_bd.phys = (u32)&rxframe;
639 rx_bd.cntrl = sizeof(rxframe);
640
641 /* Write bd to HW */
642 flush_cache((u32)&rx_bd, sizeof(rx_bd));
643
644 /* It is necessary to flush rxframe because if you don't do it
645 * then cache will contain previous packet */
646 flush_cache((u32)&rxframe, sizeof(rxframe));
647
648 /* Rx BD is ready - start again */
649 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
650
651 debug("axiemac: RX completed, framelength = %d\n", length);
652
653 return 0;
654 }
655
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)656 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
657 int devad, int reg)
658 {
659 int ret;
660 u16 value;
661
662 ret = phyread(bus->priv, addr, reg, &value);
663 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
664 value, ret);
665 return value;
666 }
667
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)668 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
669 int reg, u16 value)
670 {
671 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
672 return phywrite(bus->priv, addr, reg, value);
673 }
674
axi_emac_probe(struct udevice * dev)675 static int axi_emac_probe(struct udevice *dev)
676 {
677 struct axidma_priv *priv = dev_get_priv(dev);
678 int ret;
679
680 priv->bus = mdio_alloc();
681 priv->bus->read = axiemac_miiphy_read;
682 priv->bus->write = axiemac_miiphy_write;
683 priv->bus->priv = priv;
684
685 ret = mdio_register_seq(priv->bus, dev->seq);
686 if (ret)
687 return ret;
688
689 axiemac_phy_init(dev);
690
691 return 0;
692 }
693
axi_emac_remove(struct udevice * dev)694 static int axi_emac_remove(struct udevice *dev)
695 {
696 struct axidma_priv *priv = dev_get_priv(dev);
697
698 free(priv->phydev);
699 mdio_unregister(priv->bus);
700 mdio_free(priv->bus);
701
702 return 0;
703 }
704
705 static const struct eth_ops axi_emac_ops = {
706 .start = axiemac_start,
707 .send = axiemac_send,
708 .recv = axiemac_recv,
709 .free_pkt = axiemac_free_pkt,
710 .stop = axiemac_stop,
711 .write_hwaddr = axiemac_write_hwaddr,
712 };
713
axi_emac_ofdata_to_platdata(struct udevice * dev)714 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
715 {
716 struct eth_pdata *pdata = dev_get_platdata(dev);
717 struct axidma_priv *priv = dev_get_priv(dev);
718 int node = dev_of_offset(dev);
719 int offset = 0;
720 const char *phy_mode;
721
722 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
723 priv->iobase = (struct axi_regs *)pdata->iobase;
724
725 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
726 "axistream-connected");
727 if (offset <= 0) {
728 printf("%s: axistream is not found\n", __func__);
729 return -EINVAL;
730 }
731 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
732 offset, "reg");
733 if (!priv->dmatx) {
734 printf("%s: axi_dma register space not found\n", __func__);
735 return -EINVAL;
736 }
737 /* RX channel offset is 0x30 */
738 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
739
740 priv->phyaddr = -1;
741
742 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
743 if (offset > 0) {
744 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
745 priv->phy_of_handle = offset;
746 }
747
748 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
749 if (phy_mode)
750 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
751 if (pdata->phy_interface == -1) {
752 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
753 return -EINVAL;
754 }
755 priv->interface = pdata->phy_interface;
756
757 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
758 "xlnx,eth-hasnobuf");
759
760 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
761 priv->phyaddr, phy_string_for_interface(priv->interface));
762
763 return 0;
764 }
765
766 static const struct udevice_id axi_emac_ids[] = {
767 { .compatible = "xlnx,axi-ethernet-1.00.a" },
768 { }
769 };
770
771 U_BOOT_DRIVER(axi_emac) = {
772 .name = "axi_emac",
773 .id = UCLASS_ETH,
774 .of_match = axi_emac_ids,
775 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
776 .probe = axi_emac_probe,
777 .remove = axi_emac_remove,
778 .ops = &axi_emac_ops,
779 .priv_auto_alloc_size = sizeof(struct axidma_priv),
780 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
781 };
782