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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4  * Andreas Heppel <aheppel@sysgo.de>
5  *
6  * (C) Copyright 2002, 2003
7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8  */
9 
10 /*
11  * Old PCI routines
12  *
13  * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
14  * and change pci-uclass.c.
15  */
16 
17 #include <common.h>
18 #include <init.h>
19 
20 #include <command.h>
21 #include <env.h>
22 #include <errno.h>
23 #include <asm/processor.h>
24 #include <asm/io.h>
25 #include <pci.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 #define PCI_HOSE_OP(rw, size, type)					\
30 int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
31 				  pci_dev_t dev,			\
32 				  int offset, type value)		\
33 {									\
34 	return hose->rw##_##size(hose, dev, offset, value);		\
35 }
36 
37 PCI_HOSE_OP(read, byte, u8 *)
38 PCI_HOSE_OP(read, word, u16 *)
39 PCI_HOSE_OP(read, dword, u32 *)
40 PCI_HOSE_OP(write, byte, u8)
41 PCI_HOSE_OP(write, word, u16)
42 PCI_HOSE_OP(write, dword, u32)
43 
44 #define PCI_OP(rw, size, type, error_code)				\
45 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
46 {									\
47 	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));	\
48 									\
49 	if (!hose)							\
50 	{								\
51 		error_code;						\
52 		return -1;						\
53 	}								\
54 									\
55 	return pci_hose_##rw##_config_##size(hose, dev, offset, value);	\
56 }
57 
58 PCI_OP(read, byte, u8 *, *value = 0xff)
59 PCI_OP(read, word, u16 *, *value = 0xffff)
60 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
61 PCI_OP(write, byte, u8, )
62 PCI_OP(write, word, u16, )
63 PCI_OP(write, dword, u32, )
64 
65 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
66 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
67 					pci_dev_t dev,			\
68 					int offset, type val)		\
69 {									\
70 	u32 val32;							\
71 									\
72 	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
73 		*val = -1;						\
74 		return -1;						\
75 	}								\
76 									\
77 	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
78 									\
79 	return 0;							\
80 }
81 
82 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
83 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
84 					     pci_dev_t dev,		\
85 					     int offset, type val)	\
86 {									\
87 	u32 val32, mask, ldata, shift;					\
88 									\
89 	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
90 		return -1;						\
91 									\
92 	shift = ((offset & (int)off_mask) * 8);				\
93 	ldata = (((unsigned long)val) & val_mask) << shift;		\
94 	mask = val_mask << shift;					\
95 	val32 = (val32 & ~mask) | ldata;				\
96 									\
97 	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
98 		return -1;						\
99 									\
100 	return 0;							\
101 }
102 
103 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
104 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
105 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
106 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
107 
108 /*
109  *
110  */
111 
112 static struct pci_controller* hose_head;
113 
pci_get_hose_head(void)114 struct pci_controller *pci_get_hose_head(void)
115 {
116 	if (gd->hose)
117 		return gd->hose;
118 
119 	return hose_head;
120 }
121 
pci_register_hose(struct pci_controller * hose)122 void pci_register_hose(struct pci_controller* hose)
123 {
124 	struct pci_controller **phose = &hose_head;
125 
126 	while(*phose)
127 		phose = &(*phose)->next;
128 
129 	hose->next = NULL;
130 
131 	*phose = hose;
132 }
133 
pci_bus_to_hose(int bus)134 struct pci_controller *pci_bus_to_hose(int bus)
135 {
136 	struct pci_controller *hose;
137 
138 	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
139 		if (bus >= hose->first_busno && bus <= hose->last_busno)
140 			return hose;
141 	}
142 
143 	printf("pci_bus_to_hose() failed\n");
144 	return NULL;
145 }
146 
find_hose_by_cfg_addr(void * cfg_addr)147 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
148 {
149 	struct pci_controller *hose;
150 
151 	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
152 		if (hose->cfg_addr == cfg_addr)
153 			return hose;
154 	}
155 
156 	return NULL;
157 }
158 
pci_last_busno(void)159 int pci_last_busno(void)
160 {
161 	struct pci_controller *hose = pci_get_hose_head();
162 
163 	if (!hose)
164 		return -1;
165 
166 	while (hose->next)
167 		hose = hose->next;
168 
169 	return hose->last_busno;
170 }
171 
pci_find_devices(struct pci_device_id * ids,int index)172 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
173 {
174 	struct pci_controller * hose;
175 	pci_dev_t bdf;
176 	int bus;
177 
178 	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
179 		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
180 			bdf = pci_hose_find_devices(hose, bus, ids, &index);
181 			if (bdf != -1)
182 				return bdf;
183 		}
184 	}
185 
186 	return -1;
187 }
188 
pci_hose_config_device(struct pci_controller * hose,pci_dev_t dev,ulong io,pci_addr_t mem,ulong command)189 static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
190 				  ulong io, pci_addr_t mem, ulong command)
191 {
192 	u32 bar_response;
193 	unsigned int old_command;
194 	pci_addr_t bar_value;
195 	pci_size_t bar_size;
196 	unsigned char pin;
197 	int bar, found_mem64;
198 
199 	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
200 		(u64)mem, command);
201 
202 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
203 
204 	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
205 		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
206 		pci_hose_read_config_dword(hose, dev, bar, &bar_response);
207 
208 		if (!bar_response)
209 			continue;
210 
211 		found_mem64 = 0;
212 
213 		/* Check the BAR type and set our address mask */
214 		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
215 			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
216 			/* round up region base address to a multiple of size */
217 			io = ((io - 1) | (bar_size - 1)) + 1;
218 			bar_value = io;
219 			/* compute new region base address */
220 			io = io + bar_size;
221 		} else {
222 			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
223 				PCI_BASE_ADDRESS_MEM_TYPE_64) {
224 				u32 bar_response_upper;
225 				u64 bar64;
226 				pci_hose_write_config_dword(hose, dev, bar + 4,
227 					0xffffffff);
228 				pci_hose_read_config_dword(hose, dev, bar + 4,
229 					&bar_response_upper);
230 
231 				bar64 = ((u64)bar_response_upper << 32) | bar_response;
232 
233 				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
234 				found_mem64 = 1;
235 			} else {
236 				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
237 			}
238 
239 			/* round up region base address to multiple of size */
240 			mem = ((mem - 1) | (bar_size - 1)) + 1;
241 			bar_value = mem;
242 			/* compute new region base address */
243 			mem = mem + bar_size;
244 		}
245 
246 		/* Write it out and update our limit */
247 		pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
248 
249 		if (found_mem64) {
250 			bar += 4;
251 #ifdef CONFIG_SYS_PCI_64BIT
252 			pci_hose_write_config_dword(hose, dev, bar,
253 				(u32)(bar_value >> 32));
254 #else
255 			pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
256 #endif
257 		}
258 	}
259 
260 	/* Configure Cache Line Size Register */
261 	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
262 
263 	/* Configure Latency Timer */
264 	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
265 
266 	/* Disable interrupt line, if device says it wants to use interrupts */
267 	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
268 	if (pin != 0) {
269 		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
270 					   PCI_INTERRUPT_LINE_DISABLE);
271 	}
272 
273 	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
274 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
275 				     (old_command & 0xffff0000) | command);
276 
277 	return 0;
278 }
279 
280 /*
281  *
282  */
283 
pci_find_config(struct pci_controller * hose,unsigned short class,unsigned int vendor,unsigned int device,unsigned int bus,unsigned int dev,unsigned int func)284 struct pci_config_table *pci_find_config(struct pci_controller *hose,
285 					 unsigned short class,
286 					 unsigned int vendor,
287 					 unsigned int device,
288 					 unsigned int bus,
289 					 unsigned int dev,
290 					 unsigned int func)
291 {
292 	struct pci_config_table *table;
293 
294 	for (table = hose->config_table; table && table->vendor; table++) {
295 		if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
296 		    (table->device == PCI_ANY_ID || table->device == device) &&
297 		    (table->class  == PCI_ANY_ID || table->class  == class)  &&
298 		    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
299 		    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
300 		    (table->func   == PCI_ANY_ID || table->func   == func)) {
301 			return table;
302 		}
303 	}
304 
305 	return NULL;
306 }
307 
pci_cfgfunc_config_device(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * entry)308 void pci_cfgfunc_config_device(struct pci_controller *hose,
309 			       pci_dev_t dev,
310 			       struct pci_config_table *entry)
311 {
312 	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
313 		entry->priv[2]);
314 }
315 
pci_cfgfunc_do_nothing(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * entry)316 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
317 			    pci_dev_t dev, struct pci_config_table *entry)
318 {
319 }
320 
321 /*
322  * HJF: Changed this to return int. I think this is required
323  * to get the correct result when scanning bridges
324  */
325 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
326 
327 #ifdef CONFIG_PCI_SCAN_SHOW
pci_print_dev(struct pci_controller * hose,pci_dev_t dev)328 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
329 {
330 	if (dev == PCI_BDF(hose->first_busno, 0, 0))
331 		return 0;
332 
333 	return 1;
334 }
335 #endif /* CONFIG_PCI_SCAN_SHOW */
336 
pci_hose_scan_bus(struct pci_controller * hose,int bus)337 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
338 {
339 	unsigned int sub_bus, found_multi = 0;
340 	unsigned short vendor, device, class;
341 	unsigned char header_type;
342 #ifndef CONFIG_PCI_PNP
343 	struct pci_config_table *cfg;
344 #endif
345 	pci_dev_t dev;
346 #ifdef CONFIG_PCI_SCAN_SHOW
347 	static int indent = 0;
348 #endif
349 
350 	sub_bus = bus;
351 
352 	for (dev =  PCI_BDF(bus,0,0);
353 	     dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
354 				PCI_MAX_PCI_FUNCTIONS - 1);
355 	     dev += PCI_BDF(0, 0, 1)) {
356 
357 		if (pci_skip_dev(hose, dev))
358 			continue;
359 
360 		if (PCI_FUNC(dev) && !found_multi)
361 			continue;
362 
363 		pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
364 
365 		pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
366 
367 		if (vendor == 0xffff || vendor == 0x0000)
368 			continue;
369 
370 		if (!PCI_FUNC(dev))
371 			found_multi = header_type & 0x80;
372 
373 		debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
374 			PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
375 
376 		pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
377 		pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
378 
379 #ifdef CONFIG_PCI_FIXUP_DEV
380 		board_pci_fixup_dev(hose, dev, vendor, device, class);
381 #endif
382 
383 #ifdef CONFIG_PCI_SCAN_SHOW
384 		indent++;
385 
386 		/* Print leading space, including bus indentation */
387 		printf("%*c", indent + 1, ' ');
388 
389 		if (pci_print_dev(hose, dev)) {
390 			printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
391 			       PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
392 			       vendor, device, pci_class_str(class >> 8));
393 		}
394 #endif
395 
396 #ifdef CONFIG_PCI_PNP
397 		sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
398 			      sub_bus);
399 #else
400 		cfg = pci_find_config(hose, class, vendor, device,
401 				      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
402 		if (cfg) {
403 			cfg->config_device(hose, dev, cfg);
404 			sub_bus = max(sub_bus,
405 				      (unsigned int)hose->current_busno);
406 		}
407 #endif
408 
409 #ifdef CONFIG_PCI_SCAN_SHOW
410 		indent--;
411 #endif
412 
413 		if (hose->fixup_irq)
414 			hose->fixup_irq(hose, dev);
415 	}
416 
417 	return sub_bus;
418 }
419 
pci_hose_scan(struct pci_controller * hose)420 int pci_hose_scan(struct pci_controller *hose)
421 {
422 #if defined(CONFIG_PCI_BOOTDELAY)
423 	char *s;
424 	int i;
425 
426 	if (!gd->pcidelay_done) {
427 		/* wait "pcidelay" ms (if defined)... */
428 		s = env_get("pcidelay");
429 		if (s) {
430 			int val = simple_strtoul(s, NULL, 10);
431 			for (i = 0; i < val; i++)
432 				udelay(1000);
433 		}
434 		gd->pcidelay_done = 1;
435 	}
436 #endif /* CONFIG_PCI_BOOTDELAY */
437 
438 #ifdef CONFIG_PCI_SCAN_SHOW
439 	puts("PCI:\n");
440 #endif
441 
442 	/*
443 	 * Start scan at current_busno.
444 	 * PCIe will start scan at first_busno+1.
445 	 */
446 	/* For legacy support, ensure current >= first */
447 	if (hose->first_busno > hose->current_busno)
448 		hose->current_busno = hose->first_busno;
449 #ifdef CONFIG_PCI_PNP
450 	pciauto_config_init(hose);
451 #endif
452 	return pci_hose_scan_bus(hose, hose->current_busno);
453 }
454 
pci_init(void)455 void pci_init(void)
456 {
457 	hose_head = NULL;
458 
459 	/* allow env to disable pci init/enum */
460 	if (env_get("pcidisable") != NULL)
461 		return;
462 
463 	/* now call board specific pci_init()... */
464 	pci_init_board();
465 }
466 
467 /* Returns the address of the requested capability structure within the
468  * device's PCI configuration space or 0 in case the device does not
469  * support it.
470  * */
pci_hose_find_capability(struct pci_controller * hose,pci_dev_t dev,int cap)471 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
472 			     int cap)
473 {
474 	int pos;
475 	u8 hdr_type;
476 
477 	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
478 
479 	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
480 
481 	if (pos)
482 		pos = pci_find_cap(hose, dev, pos, cap);
483 
484 	return pos;
485 }
486 
487 /* Find the header pointer to the Capabilities*/
pci_hose_find_cap_start(struct pci_controller * hose,pci_dev_t dev,u8 hdr_type)488 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
489 			    u8 hdr_type)
490 {
491 	u16 status;
492 
493 	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
494 
495 	if (!(status & PCI_STATUS_CAP_LIST))
496 		return 0;
497 
498 	switch (hdr_type) {
499 	case PCI_HEADER_TYPE_NORMAL:
500 	case PCI_HEADER_TYPE_BRIDGE:
501 		return PCI_CAPABILITY_LIST;
502 	case PCI_HEADER_TYPE_CARDBUS:
503 		return PCI_CB_CAPABILITY_LIST;
504 	default:
505 		return 0;
506 	}
507 }
508 
pci_find_cap(struct pci_controller * hose,pci_dev_t dev,int pos,int cap)509 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
510 {
511 	int ttl = PCI_FIND_CAP_TTL;
512 	u8 id;
513 	u8 next_pos;
514 
515 	while (ttl--) {
516 		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
517 		if (next_pos < CAP_START_POS)
518 			break;
519 		next_pos &= ~3;
520 		pos = (int) next_pos;
521 		pci_hose_read_config_byte(hose, dev,
522 					  pos + PCI_CAP_LIST_ID, &id);
523 		if (id == 0xff)
524 			break;
525 		if (id == cap)
526 			return pos;
527 		pos += PCI_CAP_LIST_NEXT;
528 	}
529 	return 0;
530 }
531 
532 /**
533  * pci_find_next_ext_capability - Find an extended capability
534  *
535  * Returns the address of the next matching extended capability structure
536  * within the device's PCI configuration space or 0 if the device does
537  * not support it.  Some capabilities can occur several times, e.g., the
538  * vendor-specific capability, and this provides a way to find them all.
539  */
pci_find_next_ext_capability(struct pci_controller * hose,pci_dev_t dev,int start,int cap)540 int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
541 				 int start, int cap)
542 {
543 	u32 header;
544 	int ttl, pos = PCI_CFG_SPACE_SIZE;
545 
546 	/* minimum 8 bytes per capability */
547 	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
548 
549 	if (start)
550 		pos = start;
551 
552 	pci_hose_read_config_dword(hose, dev, pos, &header);
553 	if (header == 0xffffffff || header == 0)
554 		return 0;
555 
556 	while (ttl-- > 0) {
557 		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
558 			return pos;
559 
560 		pos = PCI_EXT_CAP_NEXT(header);
561 		if (pos < PCI_CFG_SPACE_SIZE)
562 			break;
563 
564 		pci_hose_read_config_dword(hose, dev, pos, &header);
565 		if (header == 0xffffffff || header == 0)
566 			break;
567 	}
568 
569 	return 0;
570 }
571 
572 /**
573  * pci_hose_find_ext_capability - Find an extended capability
574  *
575  * Returns the address of the requested extended capability structure
576  * within the device's PCI configuration space or 0 if the device does
577  * not support it.
578  */
pci_hose_find_ext_capability(struct pci_controller * hose,pci_dev_t dev,int cap)579 int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
580 				 int cap)
581 {
582 	return pci_find_next_ext_capability(hose, dev, 0, cap);
583 }
584