1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SH7751 PCI Controller (PCIC) for U-Boot.
4 * (C) Dustin McIntire (dustin@sensoria.com)
5 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <pci.h>
11 #include <asm/processor.h>
12 #include <asm/io.h>
13 #include <asm/pci.h>
14
15 /* Register addresses and such */
16 #define SH7751_BCR1 (vu_long *)0xFF800000
17 #define SH7751_BCR2 (vu_short *)0xFF800004
18 #define SH7751_WCR1 (vu_long *)0xFF800008
19 #define SH7751_WCR2 (vu_long *)0xFF80000C
20 #define SH7751_WCR3 (vu_long *)0xFF800010
21 #define SH7751_MCR (vu_long *)0xFF800014
22 #define SH7751_BCR3 (vu_short *)0xFF800050
23 #define SH7751_PCICONF0 (vu_long *)0xFE200000
24 #define SH7751_PCICONF1 (vu_long *)0xFE200004
25 #define SH7751_PCICONF2 (vu_long *)0xFE200008
26 #define SH7751_PCICONF3 (vu_long *)0xFE20000C
27 #define SH7751_PCICONF4 (vu_long *)0xFE200010
28 #define SH7751_PCICONF5 (vu_long *)0xFE200014
29 #define SH7751_PCICONF6 (vu_long *)0xFE200018
30 #define SH7751_PCICR (vu_long *)0xFE200100
31 #define SH7751_PCILSR0 (vu_long *)0xFE200104
32 #define SH7751_PCILSR1 (vu_long *)0xFE200108
33 #define SH7751_PCILAR0 (vu_long *)0xFE20010C
34 #define SH7751_PCILAR1 (vu_long *)0xFE200110
35 #define SH7751_PCIMBR (vu_long *)0xFE2001C4
36 #define SH7751_PCIIOBR (vu_long *)0xFE2001C8
37 #define SH7751_PCIPINT (vu_long *)0xFE2001CC
38 #define SH7751_PCIPINTM (vu_long *)0xFE2001D0
39 #define SH7751_PCICLKR (vu_long *)0xFE2001D4
40 #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
41 #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
42 #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
43 #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
44 #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
45 #define SH7751_PCIMCR (vu_long *)0xFE2001F4
46 #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
47
48 #define BCR1_BREQEN 0x00080000
49 #define PCI_SH7751_ID 0x35051054
50 #define PCI_SH7751R_ID 0x350E1054
51 #define SH7751_PCICONF1_WCC 0x00000080
52 #define SH7751_PCICONF1_PER 0x00000040
53 #define SH7751_PCICONF1_BUM 0x00000004
54 #define SH7751_PCICONF1_MES 0x00000002
55 #define SH7751_PCICONF1_CMDS 0x000000C6
56 #define SH7751_PCI_HOST_BRIDGE 0x6
57 #define SH7751_PCICR_PREFIX 0xa5000000
58 #define SH7751_PCICR_PRST 0x00000002
59 #define SH7751_PCICR_CFIN 0x00000001
60 #define SH7751_PCIPINT_D3 0x00000002
61 #define SH7751_PCIPINT_D0 0x00000001
62 #define SH7751_PCICLKR_PREFIX 0xa5000000
63
64 #define SH7751_PCI_MEM_BASE 0xFD000000
65 #define SH7751_PCI_MEM_SIZE 0x01000000
66 #define SH7751_PCI_IO_BASE 0xFE240000
67 #define SH7751_PCI_IO_SIZE 0x00040000
68
69 #define SH7751_PCIPAR (vu_long *)0xFE2001C0
70 #define SH7751_PCIPDR (vu_long *)0xFE200220
71
72 #define p4_in(addr) (*addr)
73 #define p4_out(data, addr) (*addr) = (data)
74
sh7751_pci_addr_valid(pci_dev_t d,uint offset)75 static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
76 {
77 if (PCI_FUNC(d))
78 return -EINVAL;
79
80 return 0;
81 }
82
get_bus_address(struct udevice * dev,pci_dev_t bdf,u32 offset)83 static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
84 {
85 return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
86 }
87
sh7751_pci_read_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong * value,enum pci_size_t size)88 static int sh7751_pci_read_config(struct udevice *dev, pci_dev_t bdf,
89 uint offset, ulong *value,
90 enum pci_size_t size)
91 {
92 u32 addr, reg;
93 int ret;
94
95 ret = sh7751_pci_addr_valid(bdf, offset);
96 if (ret) {
97 *value = pci_get_ff(size);
98 return 0;
99 }
100
101 addr = get_bus_address(dev, bdf, offset);
102 p4_out(addr, SH7751_PCIPAR);
103 reg = p4_in(SH7751_PCIPDR);
104 *value = pci_conv_32_to_size(reg, offset, size);
105
106 return 0;
107 }
108
sh7751_pci_write_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)109 static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
110 uint offset, ulong value,
111 enum pci_size_t size)
112 {
113 u32 addr, reg, old;
114 int ret;
115
116 ret = sh7751_pci_addr_valid(bdf, offset);
117 if (ret)
118 return ret;
119
120 addr = get_bus_address(dev, bdf, offset);
121 p4_out(addr, SH7751_PCIPAR);
122 old = p4_in(SH7751_PCIPDR);
123 reg = pci_conv_size_to_32(old, value, offset, size);
124 p4_out(reg, SH7751_PCIPDR);
125
126 return 0;
127 }
128
sh7751_pci_probe(struct udevice * dev)129 static int sh7751_pci_probe(struct udevice *dev)
130 {
131 /* Double-check that we're a 7751 or 7751R chip */
132 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
133 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
134 printf("PCI: Unknown PCI host bridge.\n");
135 return 1;
136 }
137 printf("PCI: SH7751 PCI host bridge found.\n");
138
139 /* Double-check some BSC config settings */
140 /* (Area 3 non-MPX 32-bit, PCI bus pins) */
141 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
142 printf("SH7751_BCR1 value is wrong(0x%08X)\n",
143 (unsigned int)p4_in(SH7751_BCR1));
144 return 2;
145 }
146 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
147 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
148 (unsigned int)p4_in(SH7751_BCR2));
149 return 3;
150 }
151 if (p4_in(SH7751_BCR2) & 0x01) {
152 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
153 (unsigned int)p4_in(SH7751_BCR2));
154 return 4;
155 }
156
157 /* Force BREQEN in BCR1 to allow PCIC access */
158 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
159
160 /* Toggle PCI reset pin */
161 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
162 udelay(32);
163 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
164
165 /* Set cmd bits: WCC, PER, BUM, MES */
166 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
167 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
168
169 /* Define this host as the host bridge */
170 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
171
172 /* Force PCI clock(s) on */
173 p4_out(0, SH7751_PCICLKR);
174 p4_out(0x03, SH7751_PCICLKR);
175
176 /* Clear powerdown IRQs, also mask them (unused) */
177 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
178 p4_out(0, SH7751_PCIPINTM);
179
180 p4_out(0xab000001, SH7751_PCICONF4);
181
182 /* Set up target memory mappings (for external DMA access) */
183 /* Map both P0 and P2 range to Area 3 RAM for ease of use */
184 p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
185 p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
186 p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
187
188 p4_out(0, SH7751_PCILSR1);
189 p4_out(0, SH7751_PCILAR1);
190 p4_out(0xd0000000, SH7751_PCICONF6);
191
192 /* Map memory window to same address on PCI bus */
193 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
194
195 /* Map IO window to same address on PCI bus */
196 p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
197
198 /* set BREQEN */
199 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
200
201 /* Copy BSC registers into PCI BSC */
202 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
203 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
204 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
205 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
206 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
207 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
208 p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
209
210 /* Finally, set central function init complete */
211 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
212
213 return 0;
214 }
215
216 static const struct dm_pci_ops sh7751_pci_ops = {
217 .read_config = sh7751_pci_read_config,
218 .write_config = sh7751_pci_write_config,
219 };
220
221 static const struct udevice_id sh7751_pci_ids[] = {
222 { .compatible = "renesas,pci-sh7751" },
223 { }
224 };
225
226 U_BOOT_DRIVER(sh7751_pci) = {
227 .name = "sh7751_pci",
228 .id = UCLASS_PCI,
229 .of_match = sh7751_pci_ids,
230 .ops = &sh7751_pci_ops,
231 .probe = sh7751_pci_probe,
232 };
233