1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Socfpga Reset Controller Driver
4 *
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
6 *
7 * based on
8 * Allwinner SoCs Reset Controller driver
9 *
10 * Copyright 2013 Maxime Ripard
11 *
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
13 */
14
15 #include <common.h>
16 #include <dm.h>
17 #include <dm/lists.h>
18 #include <dm/of_access.h>
19 #include <env.h>
20 #include <reset-uclass.h>
21 #include <linux/bitops.h>
22 #include <linux/io.h>
23 #include <linux/sizes.h>
24
25 #define BANK_INCREMENT 4
26 #define NR_BANKS 8
27
28 struct socfpga_reset_data {
29 void __iomem *modrst_base;
30 };
31
32 /*
33 * For compatibility with Kernels that don't support peripheral reset, this
34 * driver can keep the old behaviour of not asserting peripheral reset before
35 * starting the OS and deasserting all peripheral resets (enabling all
36 * peripherals).
37 *
38 * For that, the reset driver checks the environment variable
39 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
40 * reset again once taken out of reset and all peripherals in 'permodrst' are
41 * taken out of reset before booting into the OS.
42 * Note that this should be required for gen5 systems only that are running
43 * Linux kernels without proper peripheral reset support for all drivers used.
44 */
socfpga_reset_keep_enabled(void)45 static bool socfpga_reset_keep_enabled(void)
46 {
47 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
48 const char *env_str;
49 long val;
50
51 env_str = env_get("socfpga_legacy_reset_compat");
52 if (env_str) {
53 val = simple_strtol(env_str, NULL, 0);
54 if (val == 1)
55 return true;
56 }
57 #endif
58
59 return false;
60 }
61
socfpga_reset_assert(struct reset_ctl * reset_ctl)62 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
63 {
64 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
65 int id = reset_ctl->id;
66 int reg_width = sizeof(u32);
67 int bank = id / (reg_width * BITS_PER_BYTE);
68 int offset = id % (reg_width * BITS_PER_BYTE);
69
70 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
71 return 0;
72 }
73
socfpga_reset_deassert(struct reset_ctl * reset_ctl)74 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
75 {
76 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
77 int id = reset_ctl->id;
78 int reg_width = sizeof(u32);
79 int bank = id / (reg_width * BITS_PER_BYTE);
80 int offset = id % (reg_width * BITS_PER_BYTE);
81
82 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
83 return 0;
84 }
85
socfpga_reset_request(struct reset_ctl * reset_ctl)86 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
87 {
88 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
89 reset_ctl, reset_ctl->dev, reset_ctl->id);
90
91 return 0;
92 }
93
socfpga_reset_free(struct reset_ctl * reset_ctl)94 static int socfpga_reset_free(struct reset_ctl *reset_ctl)
95 {
96 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
97 reset_ctl->dev, reset_ctl->id);
98
99 return 0;
100 }
101
102 static const struct reset_ops socfpga_reset_ops = {
103 .request = socfpga_reset_request,
104 .free = socfpga_reset_free,
105 .rst_assert = socfpga_reset_assert,
106 .rst_deassert = socfpga_reset_deassert,
107 };
108
socfpga_reset_probe(struct udevice * dev)109 static int socfpga_reset_probe(struct udevice *dev)
110 {
111 struct socfpga_reset_data *data = dev_get_priv(dev);
112 u32 modrst_offset;
113 void __iomem *membase;
114
115 membase = devfdt_get_addr_ptr(dev);
116
117 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
118 data->modrst_base = membase + modrst_offset;
119
120 return 0;
121 }
122
socfpga_reset_remove(struct udevice * dev)123 static int socfpga_reset_remove(struct udevice *dev)
124 {
125 struct socfpga_reset_data *data = dev_get_priv(dev);
126
127 if (socfpga_reset_keep_enabled()) {
128 puts("Deasserting all peripheral resets\n");
129 writel(0, data->modrst_base + 4);
130 }
131
132 return 0;
133 }
134
socfpga_reset_bind(struct udevice * dev)135 static int socfpga_reset_bind(struct udevice *dev)
136 {
137 int ret;
138 struct udevice *sys_child;
139
140 /*
141 * The sysreset driver does not have a device node, so bind it here.
142 * Bind it to the node, too, so that it can get its base address.
143 */
144 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
145 dev->node, &sys_child);
146 if (ret)
147 debug("Warning: No sysreset driver: ret=%d\n", ret);
148
149 return 0;
150 }
151
152 static const struct udevice_id socfpga_reset_match[] = {
153 { .compatible = "altr,rst-mgr" },
154 { /* sentinel */ },
155 };
156
157 U_BOOT_DRIVER(socfpga_reset) = {
158 .name = "socfpga-reset",
159 .id = UCLASS_RESET,
160 .of_match = socfpga_reset_match,
161 .bind = socfpga_reset_bind,
162 .probe = socfpga_reset_probe,
163 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
164 .ops = &socfpga_reset_ops,
165 .remove = socfpga_reset_remove,
166 .flags = DM_FLAG_OS_PREPARE,
167 };
168