1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 */
5 #include <common.h>
6 #include <clk.h>
7 #include <dm.h>
8 #include <rtc.h>
9 #include <asm/io.h>
10 #include <linux/iopoll.h>
11
12 #define STM32_RTC_TR 0x00
13 #define STM32_RTC_DR 0x04
14 #define STM32_RTC_ISR 0x0C
15 #define STM32_RTC_PRER 0x10
16 #define STM32_RTC_CR 0x18
17 #define STM32_RTC_WPR 0x24
18
19 /* STM32_RTC_TR bit fields */
20 #define STM32_RTC_SEC_SHIFT 0
21 #define STM32_RTC_SEC GENMASK(6, 0)
22 #define STM32_RTC_MIN_SHIFT 8
23 #define STM32_RTC_MIN GENMASK(14, 8)
24 #define STM32_RTC_HOUR_SHIFT 16
25 #define STM32_RTC_HOUR GENMASK(21, 16)
26
27 /* STM32_RTC_DR bit fields */
28 #define STM32_RTC_DATE_SHIFT 0
29 #define STM32_RTC_DATE GENMASK(5, 0)
30 #define STM32_RTC_MONTH_SHIFT 8
31 #define STM32_RTC_MONTH GENMASK(12, 8)
32 #define STM32_RTC_WDAY_SHIFT 13
33 #define STM32_RTC_WDAY GENMASK(15, 13)
34 #define STM32_RTC_YEAR_SHIFT 16
35 #define STM32_RTC_YEAR GENMASK(23, 16)
36
37 /* STM32_RTC_CR bit fields */
38 #define STM32_RTC_CR_FMT BIT(6)
39
40 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
41 #define STM32_RTC_ISR_INITS BIT(4)
42 #define STM32_RTC_ISR_RSF BIT(5)
43 #define STM32_RTC_ISR_INITF BIT(6)
44 #define STM32_RTC_ISR_INIT BIT(7)
45
46 /* STM32_RTC_PRER bit fields */
47 #define STM32_RTC_PRER_PRED_S_SHIFT 0
48 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
49 #define STM32_RTC_PRER_PRED_A_SHIFT 16
50 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
51
52 /* STM32_RTC_WPR key constants */
53 #define RTC_WPR_1ST_KEY 0xCA
54 #define RTC_WPR_2ND_KEY 0x53
55 #define RTC_WPR_WRONG_KEY 0xFF
56
57 struct stm32_rtc_priv {
58 fdt_addr_t base;
59 };
60
stm32_rtc_get(struct udevice * dev,struct rtc_time * tm)61 static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
62 {
63 struct stm32_rtc_priv *priv = dev_get_priv(dev);
64 u32 tr, dr;
65
66 tr = readl(priv->base + STM32_RTC_TR);
67 dr = readl(priv->base + STM32_RTC_DR);
68
69 tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
70 tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
71 tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
72
73 tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
74 tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
75 tm->tm_year = 2000 +
76 bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
77 tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
78 tm->tm_yday = 0;
79 tm->tm_isdst = 0;
80
81 dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
82 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
83 tm->tm_hour, tm->tm_min, tm->tm_sec);
84
85 return 0;
86 }
87
stm32_rtc_unlock(struct udevice * dev)88 static void stm32_rtc_unlock(struct udevice *dev)
89 {
90 struct stm32_rtc_priv *priv = dev_get_priv(dev);
91
92 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
93 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
94 }
95
stm32_rtc_lock(struct udevice * dev)96 static void stm32_rtc_lock(struct udevice *dev)
97 {
98 struct stm32_rtc_priv *priv = dev_get_priv(dev);
99
100 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
101 }
102
stm32_rtc_enter_init_mode(struct udevice * dev)103 static int stm32_rtc_enter_init_mode(struct udevice *dev)
104 {
105 struct stm32_rtc_priv *priv = dev_get_priv(dev);
106 u32 isr = readl(priv->base + STM32_RTC_ISR);
107
108 if (!(isr & STM32_RTC_ISR_INITF)) {
109 isr |= STM32_RTC_ISR_INIT;
110 writel(isr, priv->base + STM32_RTC_ISR);
111
112 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
113 isr,
114 (isr & STM32_RTC_ISR_INITF),
115 100000);
116 }
117
118 return 0;
119 }
120
stm32_rtc_wait_sync(struct udevice * dev)121 static int stm32_rtc_wait_sync(struct udevice *dev)
122 {
123 struct stm32_rtc_priv *priv = dev_get_priv(dev);
124 u32 isr = readl(priv->base + STM32_RTC_ISR);
125
126 isr &= ~STM32_RTC_ISR_RSF;
127 writel(isr, priv->base + STM32_RTC_ISR);
128
129 /*
130 * Wait for RSF to be set to ensure the calendar registers are
131 * synchronised, it takes around 2 rtc_ck clock cycles
132 */
133 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
134 isr, (isr & STM32_RTC_ISR_RSF),
135 100000);
136 }
137
stm32_rtc_exit_init_mode(struct udevice * dev)138 static void stm32_rtc_exit_init_mode(struct udevice *dev)
139 {
140 struct stm32_rtc_priv *priv = dev_get_priv(dev);
141 u32 isr = readl(priv->base + STM32_RTC_ISR);
142
143 isr &= ~STM32_RTC_ISR_INIT;
144 writel(isr, priv->base + STM32_RTC_ISR);
145 }
146
stm32_rtc_set_time(struct udevice * dev,u32 time,u32 date)147 static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
148 {
149 struct stm32_rtc_priv *priv = dev_get_priv(dev);
150 int ret;
151
152 stm32_rtc_unlock(dev);
153
154 ret = stm32_rtc_enter_init_mode(dev);
155 if (ret)
156 goto lock;
157
158 writel(time, priv->base + STM32_RTC_TR);
159 writel(date, priv->base + STM32_RTC_DR);
160
161 stm32_rtc_exit_init_mode(dev);
162
163 ret = stm32_rtc_wait_sync(dev);
164
165 lock:
166 stm32_rtc_lock(dev);
167 return ret;
168 }
169
stm32_rtc_set(struct udevice * dev,const struct rtc_time * tm)170 static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
171 {
172 u32 t, d;
173
174 dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
175 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
176 tm->tm_hour, tm->tm_min, tm->tm_sec);
177
178 if (tm->tm_year < 2000 || tm->tm_year > 2099)
179 return -EINVAL;
180
181 /* Time in BCD format */
182 t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
183 t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
184 t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
185
186 /* Date in BCD format */
187 d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
188 d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
189 d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
190 STM32_RTC_YEAR;
191 d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
192
193 return stm32_rtc_set_time(dev, t, d);
194 }
195
stm32_rtc_reset(struct udevice * dev)196 static int stm32_rtc_reset(struct udevice *dev)
197 {
198 dev_dbg(dev, "Reset DATE\n");
199
200 return stm32_rtc_set_time(dev, 0, 0);
201 }
202
stm32_rtc_init(struct udevice * dev)203 static int stm32_rtc_init(struct udevice *dev)
204 {
205 struct stm32_rtc_priv *priv = dev_get_priv(dev);
206 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
207 unsigned int rate;
208 struct clk clk;
209 int ret;
210 u32 isr = readl(priv->base + STM32_RTC_ISR);
211
212 if (isr & STM32_RTC_ISR_INITS)
213 return 0;
214
215 ret = clk_get_by_index(dev, 1, &clk);
216 if (ret)
217 return ret;
218
219 ret = clk_enable(&clk);
220 if (ret) {
221 clk_free(&clk);
222 return ret;
223 }
224
225 rate = clk_get_rate(&clk);
226
227 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
228 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
229 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
230
231 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
232 pred_s = (rate / (pred_a + 1)) - 1;
233
234 if (((pred_s + 1) * (pred_a + 1)) == rate)
235 break;
236 }
237
238 /*
239 * Can't find a 1Hz, so give priority to RTC power consumption
240 * by choosing the higher possible value for prediv_a
241 */
242 if (pred_s > pred_s_max || pred_a > pred_a_max) {
243 pred_a = pred_a_max;
244 pred_s = (rate / (pred_a + 1)) - 1;
245 }
246
247 stm32_rtc_unlock(dev);
248
249 ret = stm32_rtc_enter_init_mode(dev);
250 if (ret) {
251 dev_err(dev,
252 "Can't enter in init mode. Prescaler config failed.\n");
253 goto unlock;
254 }
255
256 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
257 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
258 writel(prer, priv->base + STM32_RTC_PRER);
259
260 /* Force 24h time format */
261 cr = readl(priv->base + STM32_RTC_CR);
262 cr &= ~STM32_RTC_CR_FMT;
263 writel(cr, priv->base + STM32_RTC_CR);
264
265 stm32_rtc_exit_init_mode(dev);
266
267 ret = stm32_rtc_wait_sync(dev);
268
269 unlock:
270 stm32_rtc_lock(dev);
271
272 if (ret) {
273 clk_disable(&clk);
274 clk_free(&clk);
275 }
276
277 return ret;
278 }
279
stm32_rtc_probe(struct udevice * dev)280 static int stm32_rtc_probe(struct udevice *dev)
281 {
282 struct stm32_rtc_priv *priv = dev_get_priv(dev);
283 struct clk clk;
284 int ret;
285
286 priv->base = dev_read_addr(dev);
287 if (priv->base == FDT_ADDR_T_NONE)
288 return -EINVAL;
289
290 ret = clk_get_by_index(dev, 0, &clk);
291 if (ret)
292 return ret;
293
294 ret = clk_enable(&clk);
295 if (ret) {
296 clk_free(&clk);
297 return ret;
298 }
299
300 ret = stm32_rtc_init(dev);
301
302 if (ret) {
303 clk_disable(&clk);
304 clk_free(&clk);
305 }
306
307 return ret;
308 }
309
310 static const struct rtc_ops stm32_rtc_ops = {
311 .get = stm32_rtc_get,
312 .set = stm32_rtc_set,
313 .reset = stm32_rtc_reset,
314 };
315
316 static const struct udevice_id stm32_rtc_ids[] = {
317 { .compatible = "st,stm32mp1-rtc" },
318 { }
319 };
320
321 U_BOOT_DRIVER(rtc_stm32) = {
322 .name = "rtc-stm32",
323 .id = UCLASS_RTC,
324 .probe = stm32_rtc_probe,
325 .of_match = stm32_rtc_ids,
326 .ops = &stm32_rtc_ops,
327 .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),
328 };
329