1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek High-speed UART driver
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <div64.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <serial.h>
15 #include <watchdog.h>
16 #include <asm/io.h>
17 #include <asm/types.h>
18
19 struct mtk_serial_regs {
20 u32 rbr;
21 u32 ier;
22 u32 fcr;
23 u32 lcr;
24 u32 mcr;
25 u32 lsr;
26 u32 msr;
27 u32 spr;
28 u32 mdr1;
29 u32 highspeed;
30 u32 sample_count;
31 u32 sample_point;
32 u32 fracdiv_l;
33 u32 fracdiv_m;
34 u32 escape_en;
35 u32 guard;
36 u32 rx_sel;
37 };
38
39 #define thr rbr
40 #define iir fcr
41 #define dll rbr
42 #define dlm ier
43
44 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
45 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
46
47 #define UART_LSR_DR 0x01 /* Data ready */
48 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
49 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
50
51 #define UART_MCR_DTR 0x01 /* DTR */
52 #define UART_MCR_RTS 0x02 /* RTS */
53
54 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
55 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
56 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
57
58 #define UART_MCRVAL (UART_MCR_DTR | \
59 UART_MCR_RTS)
60
61 /* Clear & enable FIFOs */
62 #define UART_FCRVAL (UART_FCR_FIFO_EN | \
63 UART_FCR_RXSR | \
64 UART_FCR_TXSR)
65
66 /* the data is correct if the real baud is within 3%. */
67 #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
68 #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
69
70 struct mtk_serial_priv {
71 struct mtk_serial_regs __iomem *regs;
72 u32 clock;
73 };
74
_mtk_serial_setbrg(struct mtk_serial_priv * priv,int baud)75 static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
76 {
77 bool support_clk12m_baud115200;
78 u32 quot, samplecount, realbaud;
79
80 if ((baud <= 115200) && (priv->clock == 12000000))
81 support_clk12m_baud115200 = true;
82 else
83 support_clk12m_baud115200 = false;
84
85 if (baud <= 115200) {
86 writel(0, &priv->regs->highspeed);
87 quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
88
89 if (support_clk12m_baud115200) {
90 writel(3, &priv->regs->highspeed);
91 quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
92 if (quot == 0)
93 quot = 1;
94
95 samplecount = DIV_ROUND_CLOSEST(priv->clock,
96 quot * baud);
97 if (samplecount != 0) {
98 realbaud = priv->clock / samplecount / quot;
99 if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
100 (realbaud < BAUD_ALLOW_MIX(baud))) {
101 pr_info("baud %d can't be handled\n",
102 baud);
103 }
104 } else {
105 pr_info("samplecount is 0\n");
106 }
107 }
108 } else if (baud <= 576000) {
109 writel(2, &priv->regs->highspeed);
110
111 /* Set to next lower baudrate supported */
112 if ((baud == 500000) || (baud == 576000))
113 baud = 460800;
114 quot = DIV_ROUND_UP(priv->clock, 4 * baud);
115 } else {
116 writel(3, &priv->regs->highspeed);
117 quot = DIV_ROUND_UP(priv->clock, 256 * baud);
118 }
119
120 /* set divisor */
121 writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
122 writel(quot & 0xff, &priv->regs->dll);
123 writel((quot >> 8) & 0xff, &priv->regs->dlm);
124 writel(UART_LCR_WLS_8, &priv->regs->lcr);
125
126 if (baud > 460800) {
127 u32 tmp;
128
129 tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
130 writel(tmp - 1, &priv->regs->sample_count);
131 writel((tmp - 2) >> 1, &priv->regs->sample_point);
132 } else {
133 writel(0, &priv->regs->sample_count);
134 writel(0xff, &priv->regs->sample_point);
135 }
136
137 if (support_clk12m_baud115200) {
138 writel(samplecount - 1, &priv->regs->sample_count);
139 writel((samplecount - 2) >> 1, &priv->regs->sample_point);
140 }
141 }
142
_mtk_serial_putc(struct mtk_serial_priv * priv,const char ch)143 static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
144 {
145 if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
146 return -EAGAIN;
147
148 writel(ch, &priv->regs->thr);
149
150 if (ch == '\n')
151 WATCHDOG_RESET();
152
153 return 0;
154 }
155
_mtk_serial_getc(struct mtk_serial_priv * priv)156 static int _mtk_serial_getc(struct mtk_serial_priv *priv)
157 {
158 if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
159 return -EAGAIN;
160
161 return readl(&priv->regs->rbr);
162 }
163
_mtk_serial_pending(struct mtk_serial_priv * priv,bool input)164 static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
165 {
166 if (input)
167 return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
168 else
169 return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
170 }
171
172 #if defined(CONFIG_DM_SERIAL) && \
173 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
mtk_serial_setbrg(struct udevice * dev,int baudrate)174 static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
175 {
176 struct mtk_serial_priv *priv = dev_get_priv(dev);
177
178 _mtk_serial_setbrg(priv, baudrate);
179
180 return 0;
181 }
182
mtk_serial_putc(struct udevice * dev,const char ch)183 static int mtk_serial_putc(struct udevice *dev, const char ch)
184 {
185 struct mtk_serial_priv *priv = dev_get_priv(dev);
186
187 return _mtk_serial_putc(priv, ch);
188 }
189
mtk_serial_getc(struct udevice * dev)190 static int mtk_serial_getc(struct udevice *dev)
191 {
192 struct mtk_serial_priv *priv = dev_get_priv(dev);
193
194 return _mtk_serial_getc(priv);
195 }
196
mtk_serial_pending(struct udevice * dev,bool input)197 static int mtk_serial_pending(struct udevice *dev, bool input)
198 {
199 struct mtk_serial_priv *priv = dev_get_priv(dev);
200
201 return _mtk_serial_pending(priv, input);
202 }
203
mtk_serial_probe(struct udevice * dev)204 static int mtk_serial_probe(struct udevice *dev)
205 {
206 struct mtk_serial_priv *priv = dev_get_priv(dev);
207
208 /* Disable interrupt */
209 writel(0, &priv->regs->ier);
210
211 writel(UART_MCRVAL, &priv->regs->mcr);
212 writel(UART_FCRVAL, &priv->regs->fcr);
213
214 return 0;
215 }
216
mtk_serial_ofdata_to_platdata(struct udevice * dev)217 static int mtk_serial_ofdata_to_platdata(struct udevice *dev)
218 {
219 struct mtk_serial_priv *priv = dev_get_priv(dev);
220 fdt_addr_t addr;
221 struct clk clk;
222 int err;
223
224 addr = dev_read_addr(dev);
225 if (addr == FDT_ADDR_T_NONE)
226 return -EINVAL;
227
228 priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
229
230 err = clk_get_by_index(dev, 0, &clk);
231 if (!err) {
232 err = clk_get_rate(&clk);
233 if (!IS_ERR_VALUE(err))
234 priv->clock = err;
235 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
236 debug("mtk_serial: failed to get clock\n");
237 return err;
238 }
239
240 if (!priv->clock)
241 priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
242
243 if (!priv->clock) {
244 debug("mtk_serial: clock not defined\n");
245 return -EINVAL;
246 }
247
248 return 0;
249 }
250
251 static const struct dm_serial_ops mtk_serial_ops = {
252 .putc = mtk_serial_putc,
253 .pending = mtk_serial_pending,
254 .getc = mtk_serial_getc,
255 .setbrg = mtk_serial_setbrg,
256 };
257
258 static const struct udevice_id mtk_serial_ids[] = {
259 { .compatible = "mediatek,hsuart" },
260 { .compatible = "mediatek,mt6577-uart" },
261 { }
262 };
263
264 U_BOOT_DRIVER(serial_mtk) = {
265 .name = "serial_mtk",
266 .id = UCLASS_SERIAL,
267 .of_match = mtk_serial_ids,
268 .ofdata_to_platdata = mtk_serial_ofdata_to_platdata,
269 .priv_auto_alloc_size = sizeof(struct mtk_serial_priv),
270 .probe = mtk_serial_probe,
271 .ops = &mtk_serial_ops,
272 .flags = DM_FLAG_PRE_RELOC,
273 };
274 #else
275
276 DECLARE_GLOBAL_DATA_PTR;
277
278 #define DECLARE_HSUART_PRIV(port) \
279 static struct mtk_serial_priv mtk_hsuart##port = { \
280 .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
281 .clock = CONFIG_SYS_NS16550_CLK \
282 };
283
284 #define DECLARE_HSUART_FUNCTIONS(port) \
285 static int mtk_serial##port##_init(void) \
286 { \
287 writel(0, &mtk_hsuart##port.regs->ier); \
288 writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
289 writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
290 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
291 return 0 ; \
292 } \
293 static void mtk_serial##port##_setbrg(void) \
294 { \
295 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
296 } \
297 static int mtk_serial##port##_getc(void) \
298 { \
299 int err; \
300 do { \
301 err = _mtk_serial_getc(&mtk_hsuart##port); \
302 if (err == -EAGAIN) \
303 WATCHDOG_RESET(); \
304 } while (err == -EAGAIN); \
305 return err >= 0 ? err : 0; \
306 } \
307 static int mtk_serial##port##_tstc(void) \
308 { \
309 return _mtk_serial_pending(&mtk_hsuart##port, true); \
310 } \
311 static void mtk_serial##port##_putc(const char c) \
312 { \
313 int err; \
314 if (c == '\n') \
315 mtk_serial##port##_putc('\r'); \
316 do { \
317 err = _mtk_serial_putc(&mtk_hsuart##port, c); \
318 } while (err == -EAGAIN); \
319 } \
320 static void mtk_serial##port##_puts(const char *s) \
321 { \
322 while (*s) { \
323 mtk_serial##port##_putc(*s++); \
324 } \
325 }
326
327 /* Serial device descriptor */
328 #define INIT_HSUART_STRUCTURE(port, __name) { \
329 .name = __name, \
330 .start = mtk_serial##port##_init, \
331 .stop = NULL, \
332 .setbrg = mtk_serial##port##_setbrg, \
333 .getc = mtk_serial##port##_getc, \
334 .tstc = mtk_serial##port##_tstc, \
335 .putc = mtk_serial##port##_putc, \
336 .puts = mtk_serial##port##_puts, \
337 }
338
339 #define DECLARE_HSUART(port, __name) \
340 DECLARE_HSUART_PRIV(port); \
341 DECLARE_HSUART_FUNCTIONS(port); \
342 struct serial_device mtk_hsuart##port##_device = \
343 INIT_HSUART_STRUCTURE(port, __name);
344
345 #if !defined(CONFIG_CONS_INDEX)
346 #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
347 #error "Invalid console index value."
348 #endif
349
350 #if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
351 #error "Console port 1 defined but not configured."
352 #elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
353 #error "Console port 2 defined but not configured."
354 #elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
355 #error "Console port 3 defined but not configured."
356 #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
357 #error "Console port 4 defined but not configured."
358 #elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
359 #error "Console port 5 defined but not configured."
360 #elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
361 #error "Console port 6 defined but not configured."
362 #endif
363
364 #if defined(CONFIG_SYS_NS16550_COM1)
365 DECLARE_HSUART(1, "mtk-hsuart0");
366 #endif
367 #if defined(CONFIG_SYS_NS16550_COM2)
368 DECLARE_HSUART(2, "mtk-hsuart1");
369 #endif
370 #if defined(CONFIG_SYS_NS16550_COM3)
371 DECLARE_HSUART(3, "mtk-hsuart2");
372 #endif
373 #if defined(CONFIG_SYS_NS16550_COM4)
374 DECLARE_HSUART(4, "mtk-hsuart3");
375 #endif
376 #if defined(CONFIG_SYS_NS16550_COM5)
377 DECLARE_HSUART(5, "mtk-hsuart4");
378 #endif
379 #if defined(CONFIG_SYS_NS16550_COM6)
380 DECLARE_HSUART(6, "mtk-hsuart5");
381 #endif
382
default_serial_console(void)383 __weak struct serial_device *default_serial_console(void)
384 {
385 #if CONFIG_CONS_INDEX == 1
386 return &mtk_hsuart1_device;
387 #elif CONFIG_CONS_INDEX == 2
388 return &mtk_hsuart2_device;
389 #elif CONFIG_CONS_INDEX == 3
390 return &mtk_hsuart3_device;
391 #elif CONFIG_CONS_INDEX == 4
392 return &mtk_hsuart4_device;
393 #elif CONFIG_CONS_INDEX == 5
394 return &mtk_hsuart5_device;
395 #elif CONFIG_CONS_INDEX == 6
396 return &mtk_hsuart6_device;
397 #else
398 #error "Bad CONFIG_CONS_INDEX."
399 #endif
400 }
401
mtk_serial_initialize(void)402 void mtk_serial_initialize(void)
403 {
404 #if defined(CONFIG_SYS_NS16550_COM1)
405 serial_register(&mtk_hsuart1_device);
406 #endif
407 #if defined(CONFIG_SYS_NS16550_COM2)
408 serial_register(&mtk_hsuart2_device);
409 #endif
410 #if defined(CONFIG_SYS_NS16550_COM3)
411 serial_register(&mtk_hsuart3_device);
412 #endif
413 #if defined(CONFIG_SYS_NS16550_COM4)
414 serial_register(&mtk_hsuart4_device);
415 #endif
416 #if defined(CONFIG_SYS_NS16550_COM5)
417 serial_register(&mtk_hsuart5_device);
418 #endif
419 #if defined(CONFIG_SYS_NS16550_COM6)
420 serial_register(&mtk_hsuart6_device);
421 #endif
422 }
423
424 #endif
425
426 #ifdef CONFIG_DEBUG_UART_MTK
427
428 #include <debug_uart.h>
429
_debug_uart_init(void)430 static inline void _debug_uart_init(void)
431 {
432 struct mtk_serial_priv priv;
433
434 priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
435 priv.clock = CONFIG_DEBUG_UART_CLOCK;
436
437 writel(0, &priv.regs->ier);
438 writel(UART_MCRVAL, &priv.regs->mcr);
439 writel(UART_FCRVAL, &priv.regs->fcr);
440
441 _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
442 }
443
_debug_uart_putc(int ch)444 static inline void _debug_uart_putc(int ch)
445 {
446 struct mtk_serial_regs __iomem *regs =
447 (void *) CONFIG_DEBUG_UART_BASE;
448
449 while (!(readl(®s->lsr) & UART_LSR_THRE))
450 ;
451
452 writel(ch, ®s->thr);
453 }
454
455 DEBUG_UART_FUNCS
456
457 #endif