1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SuperH SCIF device driver.
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 */
8
9 #include <common.h>
10 #include <errno.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <asm/io.h>
14 #include <asm/processor.h>
15 #include <serial.h>
16 #include <linux/compiler.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include "serial_sh.h"
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #if defined(CONFIG_CPU_SH7780)
scif_rxfill(struct uart_port * port)23 static int scif_rxfill(struct uart_port *port)
24 {
25 return sci_in(port, SCRFDR) & 0xff;
26 }
27 #elif defined(CONFIG_CPU_SH7763)
scif_rxfill(struct uart_port * port)28 static int scif_rxfill(struct uart_port *port)
29 {
30 if ((port->mapbase == 0xffe00000) ||
31 (port->mapbase == 0xffe08000)) {
32 /* SCIF0/1*/
33 return sci_in(port, SCRFDR) & 0xff;
34 } else {
35 /* SCIF2 */
36 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
37 }
38 }
39 #else
scif_rxfill(struct uart_port * port)40 static int scif_rxfill(struct uart_port *port)
41 {
42 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
43 }
44 #endif
45
sh_serial_init_generic(struct uart_port * port)46 static void sh_serial_init_generic(struct uart_port *port)
47 {
48 sci_out(port, SCSCR , SCSCR_INIT(port));
49 sci_out(port, SCSCR , SCSCR_INIT(port));
50 sci_out(port, SCSMR, 0);
51 sci_out(port, SCSMR, 0);
52 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
53 sci_in(port, SCFCR);
54 sci_out(port, SCFCR, 0);
55 #if defined(CONFIG_RZA1)
56 sci_out(port, SCSPTR, 0x0003);
57 #endif
58 }
59
60 static void
sh_serial_setbrg_generic(struct uart_port * port,int clk,int baudrate)61 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
62 {
63 if (port->clk_mode == EXT_CLK) {
64 unsigned short dl = DL_VALUE(baudrate, clk);
65 sci_out(port, DL, dl);
66 /* Need wait: Clock * 1/dl * 1/16 */
67 udelay((1000000 * dl * 16 / clk) * 1000 + 1);
68 } else {
69 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
70 }
71 }
72
handle_error(struct uart_port * port)73 static void handle_error(struct uart_port *port)
74 {
75 sci_in(port, SCxSR);
76 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
77 sci_in(port, SCLSR);
78 sci_out(port, SCLSR, 0x00);
79 }
80
serial_raw_putc(struct uart_port * port,const char c)81 static int serial_raw_putc(struct uart_port *port, const char c)
82 {
83 /* Tx fifo is empty */
84 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
85 return -EAGAIN;
86
87 sci_out(port, SCxTDR, c);
88 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
89
90 return 0;
91 }
92
serial_rx_fifo_level(struct uart_port * port)93 static int serial_rx_fifo_level(struct uart_port *port)
94 {
95 return scif_rxfill(port);
96 }
97
sh_serial_tstc_generic(struct uart_port * port)98 static int sh_serial_tstc_generic(struct uart_port *port)
99 {
100 if (sci_in(port, SCxSR) & SCIF_ERRORS) {
101 handle_error(port);
102 return 0;
103 }
104
105 return serial_rx_fifo_level(port) ? 1 : 0;
106 }
107
serial_getc_check(struct uart_port * port)108 static int serial_getc_check(struct uart_port *port)
109 {
110 unsigned short status;
111
112 status = sci_in(port, SCxSR);
113
114 if (status & SCIF_ERRORS)
115 handle_error(port);
116 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
117 handle_error(port);
118 return status & (SCIF_DR | SCxSR_RDxF(port));
119 }
120
sh_serial_getc_generic(struct uart_port * port)121 static int sh_serial_getc_generic(struct uart_port *port)
122 {
123 unsigned short status;
124 char ch;
125
126 if (!serial_getc_check(port))
127 return -EAGAIN;
128
129 ch = sci_in(port, SCxRDR);
130 status = sci_in(port, SCxSR);
131
132 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
133
134 if (status & SCIF_ERRORS)
135 handle_error(port);
136
137 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
138 handle_error(port);
139
140 return ch;
141 }
142
143 #if CONFIG_IS_ENABLED(DM_SERIAL)
144
sh_serial_pending(struct udevice * dev,bool input)145 static int sh_serial_pending(struct udevice *dev, bool input)
146 {
147 struct uart_port *priv = dev_get_priv(dev);
148
149 return sh_serial_tstc_generic(priv);
150 }
151
sh_serial_putc(struct udevice * dev,const char ch)152 static int sh_serial_putc(struct udevice *dev, const char ch)
153 {
154 struct uart_port *priv = dev_get_priv(dev);
155
156 return serial_raw_putc(priv, ch);
157 }
158
sh_serial_getc(struct udevice * dev)159 static int sh_serial_getc(struct udevice *dev)
160 {
161 struct uart_port *priv = dev_get_priv(dev);
162
163 return sh_serial_getc_generic(priv);
164 }
165
sh_serial_setbrg(struct udevice * dev,int baudrate)166 static int sh_serial_setbrg(struct udevice *dev, int baudrate)
167 {
168 struct sh_serial_platdata *plat = dev_get_platdata(dev);
169 struct uart_port *priv = dev_get_priv(dev);
170
171 sh_serial_setbrg_generic(priv, plat->clk, baudrate);
172
173 return 0;
174 }
175
sh_serial_probe(struct udevice * dev)176 static int sh_serial_probe(struct udevice *dev)
177 {
178 struct sh_serial_platdata *plat = dev_get_platdata(dev);
179 struct uart_port *priv = dev_get_priv(dev);
180
181 priv->membase = (unsigned char *)plat->base;
182 priv->mapbase = plat->base;
183 priv->type = plat->type;
184 priv->clk_mode = plat->clk_mode;
185
186 sh_serial_init_generic(priv);
187
188 return 0;
189 }
190
191 static const struct dm_serial_ops sh_serial_ops = {
192 .putc = sh_serial_putc,
193 .pending = sh_serial_pending,
194 .getc = sh_serial_getc,
195 .setbrg = sh_serial_setbrg,
196 };
197
198 #if CONFIG_IS_ENABLED(OF_CONTROL)
199 static const struct udevice_id sh_serial_id[] ={
200 {.compatible = "renesas,sci", .data = PORT_SCI},
201 {.compatible = "renesas,scif", .data = PORT_SCIF},
202 {.compatible = "renesas,scifa", .data = PORT_SCIFA},
203 {}
204 };
205
sh_serial_ofdata_to_platdata(struct udevice * dev)206 static int sh_serial_ofdata_to_platdata(struct udevice *dev)
207 {
208 struct sh_serial_platdata *plat = dev_get_platdata(dev);
209 struct clk sh_serial_clk;
210 fdt_addr_t addr;
211 int ret;
212
213 addr = devfdt_get_addr(dev);
214 if (!addr)
215 return -EINVAL;
216
217 plat->base = addr;
218
219 ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
220 if (!ret) {
221 ret = clk_enable(&sh_serial_clk);
222 if (!ret)
223 plat->clk = clk_get_rate(&sh_serial_clk);
224 } else {
225 plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
226 "clock", 1);
227 }
228
229 plat->type = dev_get_driver_data(dev);
230 return 0;
231 }
232 #endif
233
234 U_BOOT_DRIVER(serial_sh) = {
235 .name = "serial_sh",
236 .id = UCLASS_SERIAL,
237 .of_match = of_match_ptr(sh_serial_id),
238 .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
239 .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
240 .probe = sh_serial_probe,
241 .ops = &sh_serial_ops,
242 #if !CONFIG_IS_ENABLED(OF_CONTROL)
243 .flags = DM_FLAG_PRE_RELOC,
244 #endif
245 .priv_auto_alloc_size = sizeof(struct uart_port),
246 };
247
248 #else /* CONFIG_DM_SERIAL */
249
250 #if defined(CONFIG_CONS_SCIF0)
251 # define SCIF_BASE SCIF0_BASE
252 #elif defined(CONFIG_CONS_SCIF1)
253 # define SCIF_BASE SCIF1_BASE
254 #elif defined(CONFIG_CONS_SCIF2)
255 # define SCIF_BASE SCIF2_BASE
256 #elif defined(CONFIG_CONS_SCIF3)
257 # define SCIF_BASE SCIF3_BASE
258 #elif defined(CONFIG_CONS_SCIF4)
259 # define SCIF_BASE SCIF4_BASE
260 #elif defined(CONFIG_CONS_SCIF5)
261 # define SCIF_BASE SCIF5_BASE
262 #elif defined(CONFIG_CONS_SCIF6)
263 # define SCIF_BASE SCIF6_BASE
264 #elif defined(CONFIG_CONS_SCIF7)
265 # define SCIF_BASE SCIF7_BASE
266 #elif defined(CONFIG_CONS_SCIFA0)
267 # define SCIF_BASE SCIFA0_BASE
268 #else
269 # error "Default SCIF doesn't set....."
270 #endif
271
272 #if defined(CONFIG_SCIF_A)
273 #define SCIF_BASE_PORT PORT_SCIFA
274 #elif defined(CONFIG_SCI)
275 #define SCIF_BASE_PORT PORT_SCI
276 #else
277 #define SCIF_BASE_PORT PORT_SCIF
278 #endif
279
280 static struct uart_port sh_sci = {
281 .membase = (unsigned char *)SCIF_BASE,
282 .mapbase = SCIF_BASE,
283 .type = SCIF_BASE_PORT,
284 #ifdef CONFIG_SCIF_USE_EXT_CLK
285 .clk_mode = EXT_CLK,
286 #endif
287 };
288
sh_serial_setbrg(void)289 static void sh_serial_setbrg(void)
290 {
291 DECLARE_GLOBAL_DATA_PTR;
292 struct uart_port *port = &sh_sci;
293
294 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
295 }
296
sh_serial_init(void)297 static int sh_serial_init(void)
298 {
299 struct uart_port *port = &sh_sci;
300
301 sh_serial_init_generic(port);
302 serial_setbrg();
303
304 return 0;
305 }
306
sh_serial_putc(const char c)307 static void sh_serial_putc(const char c)
308 {
309 struct uart_port *port = &sh_sci;
310
311 if (c == '\n') {
312 while (1) {
313 if (serial_raw_putc(port, '\r') != -EAGAIN)
314 break;
315 }
316 }
317 while (1) {
318 if (serial_raw_putc(port, c) != -EAGAIN)
319 break;
320 }
321 }
322
sh_serial_tstc(void)323 static int sh_serial_tstc(void)
324 {
325 struct uart_port *port = &sh_sci;
326
327 return sh_serial_tstc_generic(port);
328 }
329
sh_serial_getc(void)330 static int sh_serial_getc(void)
331 {
332 struct uart_port *port = &sh_sci;
333 int ch;
334
335 while (1) {
336 ch = sh_serial_getc_generic(port);
337 if (ch != -EAGAIN)
338 break;
339 }
340
341 return ch;
342 }
343
344 static struct serial_device sh_serial_drv = {
345 .name = "sh_serial",
346 .start = sh_serial_init,
347 .stop = NULL,
348 .setbrg = sh_serial_setbrg,
349 .putc = sh_serial_putc,
350 .puts = default_serial_puts,
351 .getc = sh_serial_getc,
352 .tstc = sh_serial_tstc,
353 };
354
sh_serial_initialize(void)355 void sh_serial_initialize(void)
356 {
357 serial_register(&sh_serial_drv);
358 }
359
default_serial_console(void)360 __weak struct serial_device *default_serial_console(void)
361 {
362 return &sh_serial_drv;
363 }
364 #endif /* CONFIG_DM_SERIAL */
365