1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Intel Broadwell I2S driver
4 *
5 * Copyright 2019 Google LLC
6 *
7 * Modified from dc i2s/broadwell/broadwell.c
8 */
9
10 #define LOG_CATEGORY UCLASS_I2S
11
12 #include <common.h>
13 #include <dm.h>
14 #include <i2s.h>
15 #include <time.h>
16 #include <asm/io.h>
17 #include "broadwell_i2s.h"
18
19 enum {
20 BDW_SHIM_START_ADDRESS = 0xfb000,
21 BDW_SSP0_START_ADDRESS = 0xfc000,
22 BDW_SSP1_START_ADDRESS = 0xfd000,
23 };
24
25 struct broadwell_i2s_priv {
26 enum frame_sync_rel_timing_t rel_timing;
27 enum frame_sync_pol_t sfrm_polarity;
28 enum end_transfer_state_t end_transfer_state;
29 enum clock_mode_t sclk_mode;
30 uint sclk_dummy_stop; /* 0-31 */
31 uint sclk_frame_width; /* 1-38 */
32 struct i2s_shim_regs *shim;
33 struct broadwell_i2s_regs *regs;
34 };
35
init_shim_csr(struct broadwell_i2s_priv * priv)36 static void init_shim_csr(struct broadwell_i2s_priv *priv)
37 {
38 /*
39 * Select SSP clock
40 * Turn off low power clock
41 * Set PIO mode
42 * Stall DSP core
43 */
44 clrsetbits_le32(&priv->shim->csr,
45 SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK,
46 SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ |
47 SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 |
48 SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL |
49 SHIM_CS_DCS_DSP32_AF32);
50 }
51
init_shim_clkctl(struct i2s_uc_priv * uc_priv,struct broadwell_i2s_priv * priv)52 static void init_shim_clkctl(struct i2s_uc_priv *uc_priv,
53 struct broadwell_i2s_priv *priv)
54 {
55 u32 clkctl = readl(&priv->shim->clkctl);
56
57 /* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */
58 clkctl &= SHIM_CLKCTL_RESERVED;
59 clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG;
60
61 /* Enable requested SSP interface */
62 if (uc_priv->id)
63 clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD;
64 else
65 clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD;
66
67 writel(clkctl, &priv->shim->clkctl);
68 }
69
init_sscr0(struct i2s_uc_priv * uc_priv,struct broadwell_i2s_priv * priv)70 static void init_sscr0(struct i2s_uc_priv *uc_priv,
71 struct broadwell_i2s_priv *priv)
72 {
73 u32 sscr0;
74 uint scale;
75
76 /* Set data size based on BPS */
77 if (uc_priv->bitspersample > 16)
78 sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT
79 | SSP_SSC0_EDSS;
80 else
81 sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT;
82
83 /* Set network mode, Stereo PSP frame format */
84 sscr0 |= SSP_SSC0_MODE_NETWORK |
85 SSP_SSC0_FRDC_STEREO |
86 SSP_SSC0_FRF_PSP |
87 SSP_SSC0_TIM |
88 SSP_SSC0_RIM |
89 SSP_SSC0_ECS_PCH |
90 SSP_SSC0_NCS_PCH |
91 SSP_SSC0_ACS_PCH;
92
93 /* Scale 24MHz MCLK */
94 scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs;
95 sscr0 |= scale << SSP_SSC0_SCR_SHIFT;
96
97 writel(sscr0, &priv->regs->sscr0);
98 }
99
init_sscr1(struct broadwell_i2s_priv * priv)100 static void init_sscr1(struct broadwell_i2s_priv *priv)
101 {
102 u32 sscr1 = readl(&priv->regs->sscr1);
103
104 sscr1 &= SSP_SSC1_RESERVED;
105
106 /* Set as I2S master */
107 sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER;
108
109 /* Enable TXD tristate behavior for PCH */
110 sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE;
111
112 /* Disable DMA Tx/Rx service request */
113 sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE;
114
115 /* Clock on during transfer */
116 sscr1 |= SSP_SSC1_SCFR;
117
118 /* Set FIFO thresholds */
119 sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT;
120 sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT;
121
122 /* Disable interrupts */
123 sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE);
124 sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT);
125
126 writel(sscr1, &priv->regs->sscr1);
127 }
128
init_sspsp(struct broadwell_i2s_priv * priv)129 static void init_sspsp(struct broadwell_i2s_priv *priv)
130 {
131 u32 sspsp = readl(&priv->regs->sspsp);
132
133 sspsp &= SSP_PSP_RESERVED;
134 sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT;
135 sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) &
136 SSP_PSP_DMYSTOP_MASK;
137 sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) &
138 SSP_PSP_EDMYSTOP_MASK;
139 sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT;
140
141 /* Frame Sync Relative Timing */
142 if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4)
143 sspsp |= SSP_PSP_FSRT;
144 else
145 sspsp &= ~SSP_PSP_FSRT;
146
147 /* Serial Frame Polarity */
148 if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH)
149 sspsp |= SSP_PSP_SFRMP;
150 else
151 sspsp &= ~SSP_PSP_SFRMP;
152
153 /* End Data Transfer State */
154 if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW)
155 sspsp &= ~SSP_PSP_ETDS;
156 else
157 sspsp |= SSP_PSP_ETDS;
158
159 writel(sspsp, &priv->regs->sspsp);
160 }
161
init_ssp_time_slot(struct broadwell_i2s_priv * priv)162 static void init_ssp_time_slot(struct broadwell_i2s_priv *priv)
163 {
164 writel(3, &priv->regs->sstsa);
165 writel(3, &priv->regs->ssrsa);
166 }
167
bdw_i2s_init(struct udevice * dev)168 static int bdw_i2s_init(struct udevice *dev)
169 {
170 struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
171 struct broadwell_i2s_priv *priv = dev_get_priv(dev);
172
173 init_shim_csr(priv);
174 init_shim_clkctl(uc_priv, priv);
175 init_sscr0(uc_priv, priv);
176 init_sscr1(priv);
177 init_sspsp(priv);
178 init_ssp_time_slot(priv);
179
180 return 0;
181 }
182
bdw_i2s_enable(struct broadwell_i2s_priv * priv)183 static void bdw_i2s_enable(struct broadwell_i2s_priv *priv)
184 {
185 setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE);
186 setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
187 }
188
bdw_i2s_disable(struct broadwell_i2s_priv * priv)189 static void bdw_i2s_disable(struct broadwell_i2s_priv *priv)
190 {
191 clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
192 clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
193 }
194
broadwell_i2s_tx_data(struct udevice * dev,void * data,uint data_size)195 static int broadwell_i2s_tx_data(struct udevice *dev, void *data,
196 uint data_size)
197 {
198 struct broadwell_i2s_priv *priv = dev_get_priv(dev);
199 u32 *ptr = data;
200
201 log_debug("data=%p, data_size=%x\n", data, data_size);
202 if (data_size < SSP_FIFO_SIZE) {
203 log_err("Invalid I2S data size\n");
204 return -ENODATA;
205 }
206
207 /* Enable I2S interface */
208 bdw_i2s_enable(priv);
209
210 /* Transfer data */
211 while (data_size > 0) {
212 ulong start = timer_get_us() + 100000;
213
214 /* Write data if transmit FIFO has room */
215 if (readl(&priv->regs->sssr) & SSP_SSS_TNF) {
216 writel(*ptr++, &priv->regs->ssdr);
217 data_size -= sizeof(*ptr);
218 } else {
219 if ((long)(timer_get_us() - start) > 0) {
220 /* Disable I2S interface */
221 bdw_i2s_disable(priv);
222 log_debug("I2S Transfer Timeout\n");
223 return -ETIMEDOUT;
224 }
225 }
226 }
227
228 /* Disable I2S interface */
229 bdw_i2s_disable(priv);
230 log_debug("done\n");
231
232 return 0;
233 }
234
broadwell_i2s_probe(struct udevice * dev)235 static int broadwell_i2s_probe(struct udevice *dev)
236 {
237 struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
238 struct broadwell_i2s_priv *priv = dev_get_priv(dev);
239 struct udevice *adsp = dev_get_parent(dev);
240 u32 bar0, offset;
241 int ret;
242
243 bar0 = dm_pci_read_bar32(adsp, 0);
244 if (!bar0) {
245 log_debug("Cannot read adsp bar0\n");
246 return -EINVAL;
247 }
248 offset = dev_read_addr_index(dev, 0);
249 if (offset == FDT_ADDR_T_NONE) {
250 log_debug("Cannot read address index 0\n");
251 return -EINVAL;
252 }
253 uc_priv->base_address = bar0 + offset;
254
255 /*
256 * Hard-code these values. If other settings are required we can add
257 * this to the device tree.
258 */
259 uc_priv->rfs = 64;
260 uc_priv->bfs = 32;
261 uc_priv->audio_pll_clk = 24 * 1000 * 1000;
262 uc_priv->samplingrate = 48000;
263 uc_priv->bitspersample = 16;
264 uc_priv->channels = 2;
265 uc_priv->id = 0;
266
267 priv->shim = (struct i2s_shim_regs *)uc_priv->base_address;
268 priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW;
269 priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW;
270 priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL;
271 priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM;
272 priv->sclk_dummy_stop = 0;
273 priv->sclk_frame_width = 31;
274
275 offset = dev_read_addr_index(dev, 1 + uc_priv->id);
276 if (offset == FDT_ADDR_T_NONE) {
277 log_debug("Cannot read address index %d\n", 1 + uc_priv->id);
278 return -EINVAL;
279 }
280 log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0,
281 uc_priv->base_address, offset);
282 priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset);
283
284 ret = bdw_i2s_init(dev);
285 if (ret)
286 return ret;
287
288 return 0;
289 }
290
291 static const struct i2s_ops broadwell_i2s_ops = {
292 .tx_data = broadwell_i2s_tx_data,
293 };
294
295 static const struct udevice_id broadwell_i2s_ids[] = {
296 { .compatible = "intel,broadwell-i2s" },
297 { }
298 };
299
300 U_BOOT_DRIVER(broadwell_i2s) = {
301 .name = "broadwell_i2s",
302 .id = UCLASS_I2S,
303 .of_match = broadwell_i2s_ids,
304 .probe = broadwell_i2s_probe,
305 .ops = &broadwell_i2s_ops,
306 .priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
307 };
308