1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 *
5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
6 */
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <reset.h>
12 #include <spi.h>
13
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <linux/bitfield.h>
17 #include <linux/iopoll.h>
18
19 /* STM32 SPI registers */
20 #define STM32_SPI_CR1 0x00
21 #define STM32_SPI_CR2 0x04
22 #define STM32_SPI_CFG1 0x08
23 #define STM32_SPI_CFG2 0x0C
24 #define STM32_SPI_SR 0x14
25 #define STM32_SPI_IFCR 0x18
26 #define STM32_SPI_TXDR 0x20
27 #define STM32_SPI_RXDR 0x30
28 #define STM32_SPI_I2SCFGR 0x50
29
30 /* STM32_SPI_CR1 bit fields */
31 #define SPI_CR1_SPE BIT(0)
32 #define SPI_CR1_MASRX BIT(8)
33 #define SPI_CR1_CSTART BIT(9)
34 #define SPI_CR1_CSUSP BIT(10)
35 #define SPI_CR1_HDDIR BIT(11)
36 #define SPI_CR1_SSI BIT(12)
37
38 /* STM32_SPI_CR2 bit fields */
39 #define SPI_CR2_TSIZE GENMASK(15, 0)
40
41 /* STM32_SPI_CFG1 bit fields */
42 #define SPI_CFG1_DSIZE GENMASK(4, 0)
43 #define SPI_CFG1_DSIZE_MIN 3
44 #define SPI_CFG1_FTHLV_SHIFT 5
45 #define SPI_CFG1_FTHLV GENMASK(8, 5)
46 #define SPI_CFG1_MBR_SHIFT 28
47 #define SPI_CFG1_MBR GENMASK(30, 28)
48 #define SPI_CFG1_MBR_MIN 0
49 #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
50
51 /* STM32_SPI_CFG2 bit fields */
52 #define SPI_CFG2_COMM_SHIFT 17
53 #define SPI_CFG2_COMM GENMASK(18, 17)
54 #define SPI_CFG2_MASTER BIT(22)
55 #define SPI_CFG2_LSBFRST BIT(23)
56 #define SPI_CFG2_CPHA BIT(24)
57 #define SPI_CFG2_CPOL BIT(25)
58 #define SPI_CFG2_SSM BIT(26)
59 #define SPI_CFG2_AFCNTR BIT(31)
60
61 /* STM32_SPI_SR bit fields */
62 #define SPI_SR_RXP BIT(0)
63 #define SPI_SR_TXP BIT(1)
64 #define SPI_SR_EOT BIT(3)
65 #define SPI_SR_TXTF BIT(4)
66 #define SPI_SR_OVR BIT(6)
67 #define SPI_SR_SUSP BIT(11)
68 #define SPI_SR_RXPLVL_SHIFT 13
69 #define SPI_SR_RXPLVL GENMASK(14, 13)
70 #define SPI_SR_RXWNE BIT(15)
71
72 /* STM32_SPI_IFCR bit fields */
73 #define SPI_IFCR_ALL GENMASK(11, 3)
74
75 /* STM32_SPI_I2SCFGR bit fields */
76 #define SPI_I2SCFGR_I2SMOD BIT(0)
77
78 #define MAX_CS_COUNT 4
79
80 /* SPI Master Baud Rate min/max divisor */
81 #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
82 #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
83
84 #define STM32_SPI_TIMEOUT_US 100000
85
86 /* SPI Communication mode */
87 #define SPI_FULL_DUPLEX 0
88 #define SPI_SIMPLEX_TX 1
89 #define SPI_SIMPLEX_RX 2
90 #define SPI_HALF_DUPLEX 3
91
92 struct stm32_spi_priv {
93 void __iomem *base;
94 struct clk clk;
95 struct reset_ctl rst_ctl;
96 struct gpio_desc cs_gpios[MAX_CS_COUNT];
97 ulong bus_clk_rate;
98 unsigned int fifo_size;
99 unsigned int cur_bpw;
100 unsigned int cur_hz;
101 unsigned int cur_xferlen; /* current transfer length in bytes */
102 unsigned int tx_len; /* number of data to be written in bytes */
103 unsigned int rx_len; /* number of data to be read in bytes */
104 const void *tx_buf; /* data to be written, or NULL */
105 void *rx_buf; /* data to be read, or NULL */
106 u32 cur_mode;
107 bool cs_high;
108 };
109
stm32_spi_write_txfifo(struct stm32_spi_priv * priv)110 static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
111 {
112 while ((priv->tx_len > 0) &&
113 (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
114 u32 offs = priv->cur_xferlen - priv->tx_len;
115
116 if (priv->tx_len >= sizeof(u32) &&
117 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
118 const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
119
120 writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
121 priv->tx_len -= sizeof(u32);
122 } else if (priv->tx_len >= sizeof(u16) &&
123 IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
124 const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
125
126 writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
127 priv->tx_len -= sizeof(u16);
128 } else {
129 const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
130
131 writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
132 priv->tx_len -= sizeof(u8);
133 }
134 }
135
136 debug("%s: %d bytes left\n", __func__, priv->tx_len);
137 }
138
stm32_spi_read_rxfifo(struct stm32_spi_priv * priv)139 static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
140 {
141 u32 sr = readl(priv->base + STM32_SPI_SR);
142 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
143
144 while ((priv->rx_len > 0) &&
145 ((sr & SPI_SR_RXP) ||
146 ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
147 u32 offs = priv->cur_xferlen - priv->rx_len;
148
149 if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
150 (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
151 u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
152
153 *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
154 priv->rx_len -= sizeof(u32);
155 } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
156 (priv->rx_len >= sizeof(u16) ||
157 (!(sr & SPI_SR_RXWNE) &&
158 (rxplvl >= 2 || priv->cur_bpw > 8)))) {
159 u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
160
161 *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
162 priv->rx_len -= sizeof(u16);
163 } else {
164 u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
165
166 *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
167 priv->rx_len -= sizeof(u8);
168 }
169
170 sr = readl(priv->base + STM32_SPI_SR);
171 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
172 }
173
174 debug("%s: %d bytes left\n", __func__, priv->rx_len);
175 }
176
stm32_spi_enable(struct stm32_spi_priv * priv)177 static int stm32_spi_enable(struct stm32_spi_priv *priv)
178 {
179 debug("%s\n", __func__);
180
181 /* Enable the SPI hardware */
182 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
183
184 return 0;
185 }
186
stm32_spi_disable(struct stm32_spi_priv * priv)187 static int stm32_spi_disable(struct stm32_spi_priv *priv)
188 {
189 debug("%s\n", __func__);
190
191 /* Disable the SPI hardware */
192 clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
193
194 return 0;
195 }
196
stm32_spi_claim_bus(struct udevice * slave)197 static int stm32_spi_claim_bus(struct udevice *slave)
198 {
199 struct udevice *bus = dev_get_parent(slave);
200 struct stm32_spi_priv *priv = dev_get_priv(bus);
201
202 debug("%s\n", __func__);
203
204 /* Enable the SPI hardware */
205 return stm32_spi_enable(priv);
206 }
207
stm32_spi_release_bus(struct udevice * slave)208 static int stm32_spi_release_bus(struct udevice *slave)
209 {
210 struct udevice *bus = dev_get_parent(slave);
211 struct stm32_spi_priv *priv = dev_get_priv(bus);
212
213 debug("%s\n", __func__);
214
215 /* Disable the SPI hardware */
216 return stm32_spi_disable(priv);
217 }
218
stm32_spi_stopxfer(struct udevice * dev)219 static void stm32_spi_stopxfer(struct udevice *dev)
220 {
221 struct stm32_spi_priv *priv = dev_get_priv(dev);
222 u32 cr1, sr;
223 int ret;
224
225 debug("%s\n", __func__);
226
227 cr1 = readl(priv->base + STM32_SPI_CR1);
228
229 if (!(cr1 & SPI_CR1_SPE))
230 return;
231
232 /* Wait on EOT or suspend the flow */
233 ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
234 !(sr & SPI_SR_EOT), 100000);
235 if (ret < 0) {
236 if (cr1 & SPI_CR1_CSTART) {
237 writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
238 if (readl_poll_timeout(priv->base + STM32_SPI_SR,
239 sr, !(sr & SPI_SR_SUSP),
240 100000) < 0)
241 dev_err(dev, "Suspend request timeout\n");
242 }
243 }
244
245 /* clear status flags */
246 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
247 }
248
stm32_spi_set_cs(struct udevice * dev,unsigned int cs,bool enable)249 static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
250 {
251 struct stm32_spi_priv *priv = dev_get_priv(dev);
252
253 debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
254
255 if (cs >= MAX_CS_COUNT)
256 return -ENODEV;
257
258 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
259 return -EINVAL;
260
261 if (priv->cs_high)
262 enable = !enable;
263
264 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
265 }
266
stm32_spi_set_mode(struct udevice * bus,uint mode)267 static int stm32_spi_set_mode(struct udevice *bus, uint mode)
268 {
269 struct stm32_spi_priv *priv = dev_get_priv(bus);
270 u32 cfg2_clrb = 0, cfg2_setb = 0;
271
272 debug("%s: mode=%d\n", __func__, mode);
273
274 if (mode & SPI_CPOL)
275 cfg2_setb |= SPI_CFG2_CPOL;
276 else
277 cfg2_clrb |= SPI_CFG2_CPOL;
278
279 if (mode & SPI_CPHA)
280 cfg2_setb |= SPI_CFG2_CPHA;
281 else
282 cfg2_clrb |= SPI_CFG2_CPHA;
283
284 if (mode & SPI_LSB_FIRST)
285 cfg2_setb |= SPI_CFG2_LSBFRST;
286 else
287 cfg2_clrb |= SPI_CFG2_LSBFRST;
288
289 if (cfg2_clrb || cfg2_setb)
290 clrsetbits_le32(priv->base + STM32_SPI_CFG2,
291 cfg2_clrb, cfg2_setb);
292
293 if (mode & SPI_CS_HIGH)
294 priv->cs_high = true;
295 else
296 priv->cs_high = false;
297 return 0;
298 }
299
stm32_spi_set_fthlv(struct udevice * dev,u32 xfer_len)300 static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
301 {
302 struct stm32_spi_priv *priv = dev_get_priv(dev);
303 u32 fthlv, half_fifo;
304
305 /* data packet should not exceed 1/2 of fifo space */
306 half_fifo = (priv->fifo_size / 2);
307
308 /* data_packet should not exceed transfer length */
309 fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
310
311 /* align packet size with data registers access */
312 fthlv -= (fthlv % 4);
313
314 if (!fthlv)
315 fthlv = 1;
316 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
317 (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
318
319 return 0;
320 }
321
stm32_spi_set_speed(struct udevice * bus,uint hz)322 static int stm32_spi_set_speed(struct udevice *bus, uint hz)
323 {
324 struct stm32_spi_priv *priv = dev_get_priv(bus);
325 u32 mbrdiv;
326 long div;
327
328 debug("%s: hz=%d\n", __func__, hz);
329
330 if (priv->cur_hz == hz)
331 return 0;
332
333 div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
334
335 if (div < STM32_MBR_DIV_MIN ||
336 div > STM32_MBR_DIV_MAX)
337 return -EINVAL;
338
339 /* Determine the first power of 2 greater than or equal to div */
340 if (div & (div - 1))
341 mbrdiv = fls(div);
342 else
343 mbrdiv = fls(div) - 1;
344
345 if (!mbrdiv)
346 return -EINVAL;
347
348 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
349 (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
350
351 priv->cur_hz = hz;
352
353 return 0;
354 }
355
stm32_spi_xfer(struct udevice * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)356 static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
357 const void *dout, void *din, unsigned long flags)
358 {
359 struct udevice *bus = dev_get_parent(slave);
360 struct dm_spi_slave_platdata *slave_plat;
361 struct stm32_spi_priv *priv = dev_get_priv(bus);
362 u32 sr;
363 u32 ifcr = 0;
364 u32 xferlen;
365 u32 mode;
366 int xfer_status = 0;
367
368 xferlen = bitlen / 8;
369
370 if (xferlen <= SPI_CR2_TSIZE)
371 writel(xferlen, priv->base + STM32_SPI_CR2);
372 else
373 return -EMSGSIZE;
374
375 priv->tx_buf = dout;
376 priv->rx_buf = din;
377 priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
378 priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
379
380 mode = SPI_FULL_DUPLEX;
381 if (!priv->tx_buf)
382 mode = SPI_SIMPLEX_RX;
383 else if (!priv->rx_buf)
384 mode = SPI_SIMPLEX_TX;
385
386 if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
387 priv->cur_mode = mode;
388 priv->cur_xferlen = xferlen;
389
390 /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
391 stm32_spi_disable(priv);
392
393 clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
394 mode << SPI_CFG2_COMM_SHIFT);
395
396 stm32_spi_set_fthlv(bus, xferlen);
397
398 /* Enable the SPI hardware */
399 stm32_spi_enable(priv);
400 }
401
402 debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
403 priv->tx_len, priv->rx_len);
404
405 slave_plat = dev_get_parent_platdata(slave);
406 if (flags & SPI_XFER_BEGIN)
407 stm32_spi_set_cs(bus, slave_plat->cs, false);
408
409 /* Be sure to have data in fifo before starting data transfer */
410 if (priv->tx_buf)
411 stm32_spi_write_txfifo(priv);
412
413 setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
414
415 while (1) {
416 sr = readl(priv->base + STM32_SPI_SR);
417
418 if (sr & SPI_SR_OVR) {
419 dev_err(bus, "Overrun: RX data lost\n");
420 xfer_status = -EIO;
421 break;
422 }
423
424 if (sr & SPI_SR_SUSP) {
425 dev_warn(bus, "System too slow is limiting data throughput\n");
426
427 if (priv->rx_buf && priv->rx_len > 0)
428 stm32_spi_read_rxfifo(priv);
429
430 ifcr |= SPI_SR_SUSP;
431 }
432
433 if (sr & SPI_SR_TXTF)
434 ifcr |= SPI_SR_TXTF;
435
436 if (sr & SPI_SR_TXP)
437 if (priv->tx_buf && priv->tx_len > 0)
438 stm32_spi_write_txfifo(priv);
439
440 if (sr & SPI_SR_RXP)
441 if (priv->rx_buf && priv->rx_len > 0)
442 stm32_spi_read_rxfifo(priv);
443
444 if (sr & SPI_SR_EOT) {
445 if (priv->rx_buf && priv->rx_len > 0)
446 stm32_spi_read_rxfifo(priv);
447 break;
448 }
449
450 writel(ifcr, priv->base + STM32_SPI_IFCR);
451 }
452
453 /* clear status flags */
454 setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
455 stm32_spi_stopxfer(bus);
456
457 if (flags & SPI_XFER_END)
458 stm32_spi_set_cs(bus, slave_plat->cs, true);
459
460 return xfer_status;
461 }
462
stm32_spi_get_fifo_size(struct udevice * dev)463 static int stm32_spi_get_fifo_size(struct udevice *dev)
464 {
465 struct stm32_spi_priv *priv = dev_get_priv(dev);
466 u32 count = 0;
467
468 stm32_spi_enable(priv);
469
470 while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
471 writeb(++count, priv->base + STM32_SPI_TXDR);
472
473 stm32_spi_disable(priv);
474
475 debug("%s %d x 8-bit fifo size\n", __func__, count);
476
477 return count;
478 }
479
stm32_spi_probe(struct udevice * dev)480 static int stm32_spi_probe(struct udevice *dev)
481 {
482 struct stm32_spi_priv *priv = dev_get_priv(dev);
483 unsigned long clk_rate;
484 int ret;
485 unsigned int i;
486
487 priv->base = dev_remap_addr(dev);
488 if (!priv->base)
489 return -EINVAL;
490
491 /* enable clock */
492 ret = clk_get_by_index(dev, 0, &priv->clk);
493 if (ret < 0)
494 return ret;
495
496 ret = clk_enable(&priv->clk);
497 if (ret < 0)
498 return ret;
499
500 clk_rate = clk_get_rate(&priv->clk);
501 if (!clk_rate) {
502 ret = -EINVAL;
503 goto clk_err;
504 }
505
506 priv->bus_clk_rate = clk_rate;
507
508 /* perform reset */
509 ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
510 if (ret < 0)
511 goto clk_err;
512
513 reset_assert(&priv->rst_ctl);
514 udelay(2);
515 reset_deassert(&priv->rst_ctl);
516
517 ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
518 ARRAY_SIZE(priv->cs_gpios), 0);
519 if (ret < 0) {
520 pr_err("Can't get %s cs gpios: %d", dev->name, ret);
521 goto reset_err;
522 }
523
524 priv->fifo_size = stm32_spi_get_fifo_size(dev);
525
526 priv->cur_mode = SPI_FULL_DUPLEX;
527 priv->cur_xferlen = 0;
528 priv->cur_bpw = SPI_DEFAULT_WORDLEN;
529 clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
530 priv->cur_bpw - 1);
531
532 for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
533 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
534 continue;
535
536 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
537 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
538 }
539
540 /* Ensure I2SMOD bit is kept cleared */
541 clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
542
543 /*
544 * - SS input value high
545 * - transmitter half duplex direction
546 * - automatic communication suspend when RX-Fifo is full
547 */
548 setbits_le32(priv->base + STM32_SPI_CR1,
549 SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
550
551 /*
552 * - Set the master mode (default Motorola mode)
553 * - Consider 1 master/n slaves configuration and
554 * SS input value is determined by the SSI bit
555 * - keep control of all associated GPIOs
556 */
557 setbits_le32(priv->base + STM32_SPI_CFG2,
558 SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
559
560 return 0;
561
562 reset_err:
563 reset_free(&priv->rst_ctl);
564
565 clk_err:
566 clk_disable(&priv->clk);
567 clk_free(&priv->clk);
568
569 return ret;
570 };
571
stm32_spi_remove(struct udevice * dev)572 static int stm32_spi_remove(struct udevice *dev)
573 {
574 struct stm32_spi_priv *priv = dev_get_priv(dev);
575 int ret;
576
577 stm32_spi_stopxfer(dev);
578 stm32_spi_disable(priv);
579
580 ret = reset_assert(&priv->rst_ctl);
581 if (ret < 0)
582 return ret;
583
584 reset_free(&priv->rst_ctl);
585
586 ret = clk_disable(&priv->clk);
587 if (ret < 0)
588 return ret;
589
590 clk_free(&priv->clk);
591
592 return ret;
593 };
594
595 static const struct dm_spi_ops stm32_spi_ops = {
596 .claim_bus = stm32_spi_claim_bus,
597 .release_bus = stm32_spi_release_bus,
598 .set_mode = stm32_spi_set_mode,
599 .set_speed = stm32_spi_set_speed,
600 .xfer = stm32_spi_xfer,
601 };
602
603 static const struct udevice_id stm32_spi_ids[] = {
604 { .compatible = "st,stm32h7-spi", },
605 { }
606 };
607
608 U_BOOT_DRIVER(stm32_spi) = {
609 .name = "stm32_spi",
610 .id = UCLASS_SPI,
611 .of_match = stm32_spi_ids,
612 .ops = &stm32_spi_ops,
613 .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
614 .probe = stm32_spi_probe,
615 .remove = stm32_spi_remove,
616 };
617