1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * TI QSPI driver
4 *
5 * Copyright (C) 2013, Texas Instruments, Incorporated
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <asm/io.h>
11 #include <asm/arch/omap.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <spi-mem.h>
15 #include <dm.h>
16 #include <asm/gpio.h>
17 #include <asm/omap_gpio.h>
18 #include <asm/omap_common.h>
19 #include <asm/ti-common/ti-edma3.h>
20 #include <linux/kernel.h>
21 #include <regmap.h>
22 #include <syscon.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /* ti qpsi register bit masks */
27 #define QSPI_TIMEOUT 2000000
28 #define QSPI_FCLK 192000000
29 #define QSPI_DRA7XX_FCLK 76800000
30 #define QSPI_WLEN_MAX_BITS 128
31 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
32 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
33 /* clock control */
34 #define QSPI_CLK_EN BIT(31)
35 #define QSPI_CLK_DIV_MAX 0xffff
36 /* command */
37 #define QSPI_EN_CS(n) (n << 28)
38 #define QSPI_WLEN(n) ((n-1) << 19)
39 #define QSPI_3_PIN BIT(18)
40 #define QSPI_RD_SNGL BIT(16)
41 #define QSPI_WR_SNGL (2 << 16)
42 #define QSPI_INVAL (4 << 16)
43 #define QSPI_RD_QUAD (7 << 16)
44 /* device control */
45 #define QSPI_CKPHA(n) (1 << (2 + n*8))
46 #define QSPI_CSPOL(n) (1 << (1 + n*8))
47 #define QSPI_CKPOL(n) (1 << (n*8))
48 /* status */
49 #define QSPI_WC BIT(1)
50 #define QSPI_BUSY BIT(0)
51 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
52 #define QSPI_XFER_DONE QSPI_WC
53 #define MM_SWITCH 0x01
54 #define MEM_CS(cs) ((cs + 1) << 8)
55 #define MEM_CS_UNSELECT 0xfffff8ff
56
57 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
58 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
59 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
60 #define QSPI_SETUP0_ADDR_SHIFT (8)
61 #define QSPI_SETUP0_DBITS_SHIFT (10)
62
63 /* ti qspi register set */
64 struct ti_qspi_regs {
65 u32 pid;
66 u32 pad0[3];
67 u32 sysconfig;
68 u32 pad1[3];
69 u32 int_stat_raw;
70 u32 int_stat_en;
71 u32 int_en_set;
72 u32 int_en_ctlr;
73 u32 intc_eoi;
74 u32 pad2[3];
75 u32 clk_ctrl;
76 u32 dc;
77 u32 cmd;
78 u32 status;
79 u32 data;
80 u32 setup0;
81 u32 setup1;
82 u32 setup2;
83 u32 setup3;
84 u32 memswitch;
85 u32 data1;
86 u32 data2;
87 u32 data3;
88 };
89
90 /* ti qspi priv */
91 struct ti_qspi_priv {
92 void *memory_map;
93 size_t mmap_size;
94 uint max_hz;
95 u32 num_cs;
96 struct ti_qspi_regs *base;
97 void *ctrl_mod_mmap;
98 ulong fclk;
99 unsigned int mode;
100 u32 cmd;
101 u32 dc;
102 };
103
ti_qspi_set_speed(struct udevice * bus,uint hz)104 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
105 {
106 struct ti_qspi_priv *priv = dev_get_priv(bus);
107 uint clk_div;
108
109 if (!hz)
110 clk_div = 0;
111 else
112 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
113
114 /* truncate clk_div value to QSPI_CLK_DIV_MAX */
115 if (clk_div > QSPI_CLK_DIV_MAX)
116 clk_div = QSPI_CLK_DIV_MAX;
117
118 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
119
120 /* disable SCLK */
121 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
122 &priv->base->clk_ctrl);
123 /* enable SCLK and program the clk divider */
124 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
125
126 return 0;
127 }
128
ti_qspi_cs_deactivate(struct ti_qspi_priv * priv)129 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
130 {
131 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
132 /* dummy readl to ensure bus sync */
133 readl(&priv->base->cmd);
134 }
135
ti_qspi_ctrl_mode_mmap(void * ctrl_mod_mmap,int cs,bool enable)136 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
137 {
138 u32 val;
139
140 val = readl(ctrl_mod_mmap);
141 if (enable)
142 val |= MEM_CS(cs);
143 else
144 val &= MEM_CS_UNSELECT;
145 writel(val, ctrl_mod_mmap);
146 }
147
ti_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)148 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
149 const void *dout, void *din, unsigned long flags)
150 {
151 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
152 struct ti_qspi_priv *priv;
153 struct udevice *bus;
154 uint words = bitlen >> 3; /* fixed 8-bit word length */
155 const uchar *txp = dout;
156 uchar *rxp = din;
157 uint status;
158 int timeout;
159 unsigned int cs = slave->cs;
160
161 bus = dev->parent;
162 priv = dev_get_priv(bus);
163
164 if (cs > priv->num_cs) {
165 debug("invalid qspi chip select\n");
166 return -EINVAL;
167 }
168
169 if (bitlen == 0)
170 return -1;
171
172 if (bitlen % 8) {
173 debug("spi_xfer: Non byte aligned SPI transfer\n");
174 return -1;
175 }
176
177 /* Setup command reg */
178 priv->cmd = 0;
179 priv->cmd |= QSPI_WLEN(8);
180 priv->cmd |= QSPI_EN_CS(cs);
181 if (priv->mode & SPI_3WIRE)
182 priv->cmd |= QSPI_3_PIN;
183 priv->cmd |= 0xfff;
184
185 while (words) {
186 u8 xfer_len = 0;
187
188 if (txp) {
189 u32 cmd = priv->cmd;
190
191 if (words >= QSPI_WLEN_MAX_BYTES) {
192 u32 *txbuf = (u32 *)txp;
193 u32 data;
194
195 data = cpu_to_be32(*txbuf++);
196 writel(data, &priv->base->data3);
197 data = cpu_to_be32(*txbuf++);
198 writel(data, &priv->base->data2);
199 data = cpu_to_be32(*txbuf++);
200 writel(data, &priv->base->data1);
201 data = cpu_to_be32(*txbuf++);
202 writel(data, &priv->base->data);
203 cmd &= ~QSPI_WLEN_MASK;
204 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
205 xfer_len = QSPI_WLEN_MAX_BYTES;
206 } else {
207 writeb(*txp, &priv->base->data);
208 xfer_len = 1;
209 }
210 debug("tx cmd %08x dc %08x\n",
211 cmd | QSPI_WR_SNGL, priv->dc);
212 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
213 status = readl(&priv->base->status);
214 timeout = QSPI_TIMEOUT;
215 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
216 if (--timeout < 0) {
217 printf("spi_xfer: TX timeout!\n");
218 return -1;
219 }
220 status = readl(&priv->base->status);
221 }
222 txp += xfer_len;
223 debug("tx done, status %08x\n", status);
224 }
225 if (rxp) {
226 debug("rx cmd %08x dc %08x\n",
227 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
228 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
229 status = readl(&priv->base->status);
230 timeout = QSPI_TIMEOUT;
231 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
232 if (--timeout < 0) {
233 printf("spi_xfer: RX timeout!\n");
234 return -1;
235 }
236 status = readl(&priv->base->status);
237 }
238 *rxp++ = readl(&priv->base->data);
239 xfer_len = 1;
240 debug("rx done, status %08x, read %02x\n",
241 status, *(rxp-1));
242 }
243 words -= xfer_len;
244 }
245
246 /* Terminate frame */
247 if (flags & SPI_XFER_END)
248 ti_qspi_cs_deactivate(priv);
249
250 return 0;
251 }
252
253 /* TODO: control from sf layer to here through dm-spi */
ti_qspi_copy_mmap(void * data,void * offset,size_t len)254 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
255 {
256 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
257 unsigned int addr = (unsigned int) (data);
258 unsigned int edma_slot_num = 1;
259
260 /* Invalidate the area, so no writeback into the RAM races with DMA */
261 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
262
263 /* enable edma3 clocks */
264 enable_edma3_clocks();
265
266 /* Call edma3 api to do actual DMA transfer */
267 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
268
269 /* disable edma3 clocks */
270 disable_edma3_clocks();
271 #else
272 memcpy_fromio(data, offset, len);
273 #endif
274
275 *((unsigned int *)offset) += len;
276 }
277
ti_qspi_setup_mmap_read(struct ti_qspi_priv * priv,u8 opcode,u8 data_nbits,u8 addr_width,u8 dummy_bytes)278 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
279 u8 data_nbits, u8 addr_width,
280 u8 dummy_bytes)
281 {
282 u32 memval = opcode;
283
284 switch (data_nbits) {
285 case 4:
286 memval |= QSPI_SETUP0_READ_QUAD;
287 break;
288 case 2:
289 memval |= QSPI_SETUP0_READ_DUAL;
290 break;
291 default:
292 memval |= QSPI_SETUP0_READ_NORMAL;
293 break;
294 }
295
296 memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
297 dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
298
299 writel(memval, &priv->base->setup0);
300 }
301
ti_qspi_set_mode(struct udevice * bus,uint mode)302 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
303 {
304 struct ti_qspi_priv *priv = dev_get_priv(bus);
305
306 priv->dc = 0;
307 if (mode & SPI_CPHA)
308 priv->dc |= QSPI_CKPHA(0);
309 if (mode & SPI_CPOL)
310 priv->dc |= QSPI_CKPOL(0);
311 if (mode & SPI_CS_HIGH)
312 priv->dc |= QSPI_CSPOL(0);
313
314 return 0;
315 }
316
ti_qspi_exec_mem_op(struct spi_slave * slave,const struct spi_mem_op * op)317 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
318 const struct spi_mem_op *op)
319 {
320 struct ti_qspi_priv *priv;
321 struct udevice *bus;
322
323 bus = slave->dev->parent;
324 priv = dev_get_priv(bus);
325 u32 from = 0;
326 int ret = 0;
327
328 /* Only optimize read path. */
329 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
330 !op->addr.nbytes || op->addr.nbytes > 4)
331 return -ENOTSUPP;
332
333 /* Address exceeds MMIO window size, fall back to regular mode. */
334 from = op->addr.val;
335 if (from + op->data.nbytes > priv->mmap_size)
336 return -ENOTSUPP;
337
338 ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
339 op->addr.nbytes, op->dummy.nbytes);
340
341 ti_qspi_copy_mmap((void *)op->data.buf.in,
342 (void *)priv->memory_map + from, op->data.nbytes);
343
344 return ret;
345 }
346
ti_qspi_claim_bus(struct udevice * dev)347 static int ti_qspi_claim_bus(struct udevice *dev)
348 {
349 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
350 struct ti_qspi_priv *priv;
351 struct udevice *bus;
352
353 bus = dev->parent;
354 priv = dev_get_priv(bus);
355
356 if (slave_plat->cs > priv->num_cs) {
357 debug("invalid qspi chip select\n");
358 return -EINVAL;
359 }
360
361 writel(MM_SWITCH, &priv->base->memswitch);
362 if (priv->ctrl_mod_mmap)
363 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
364 slave_plat->cs, true);
365
366 writel(priv->dc, &priv->base->dc);
367 writel(0, &priv->base->cmd);
368 writel(0, &priv->base->data);
369
370 priv->dc <<= slave_plat->cs * 8;
371 writel(priv->dc, &priv->base->dc);
372
373 return 0;
374 }
375
ti_qspi_release_bus(struct udevice * dev)376 static int ti_qspi_release_bus(struct udevice *dev)
377 {
378 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
379 struct ti_qspi_priv *priv;
380 struct udevice *bus;
381
382 bus = dev->parent;
383 priv = dev_get_priv(bus);
384
385 writel(~MM_SWITCH, &priv->base->memswitch);
386 if (priv->ctrl_mod_mmap)
387 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
388 slave_plat->cs, false);
389
390 writel(0, &priv->base->dc);
391 writel(0, &priv->base->cmd);
392 writel(0, &priv->base->data);
393 writel(0, &priv->base->setup0);
394
395 return 0;
396 }
397
ti_qspi_probe(struct udevice * bus)398 static int ti_qspi_probe(struct udevice *bus)
399 {
400 struct ti_qspi_priv *priv = dev_get_priv(bus);
401
402 priv->fclk = dev_get_driver_data(bus);
403
404 return 0;
405 }
406
map_syscon_chipselects(struct udevice * bus)407 static void *map_syscon_chipselects(struct udevice *bus)
408 {
409 #if CONFIG_IS_ENABLED(SYSCON)
410 struct udevice *syscon;
411 struct regmap *regmap;
412 const fdt32_t *cell;
413 int len, err;
414
415 err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
416 "syscon-chipselects", &syscon);
417 if (err) {
418 debug("%s: unable to find syscon device (%d)\n", __func__,
419 err);
420 return NULL;
421 }
422
423 regmap = syscon_get_regmap(syscon);
424 if (IS_ERR(regmap)) {
425 debug("%s: unable to find regmap (%ld)\n", __func__,
426 PTR_ERR(regmap));
427 return NULL;
428 }
429
430 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
431 "syscon-chipselects", &len);
432 if (len < 2*sizeof(fdt32_t)) {
433 debug("%s: offset not available\n", __func__);
434 return NULL;
435 }
436
437 return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
438 #else
439 fdt_addr_t addr;
440 addr = devfdt_get_addr_index(bus, 2);
441 return (addr == FDT_ADDR_T_NONE) ? NULL :
442 map_physmem(addr, 0, MAP_NOCACHE);
443 #endif
444 }
445
ti_qspi_ofdata_to_platdata(struct udevice * bus)446 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
447 {
448 struct ti_qspi_priv *priv = dev_get_priv(bus);
449 const void *blob = gd->fdt_blob;
450 int node = dev_of_offset(bus);
451 fdt_addr_t mmap_addr;
452 fdt_addr_t mmap_size;
453
454 priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
455 priv->base = map_physmem(devfdt_get_addr(bus),
456 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
457 mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
458 priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
459 priv->mmap_size = mmap_size;
460
461 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
462 if (priv->max_hz < 0) {
463 debug("Error: Max frequency missing\n");
464 return -ENODEV;
465 }
466 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
467
468 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
469 (int)priv->base, priv->max_hz);
470
471 return 0;
472 }
473
474 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
475 .exec_op = ti_qspi_exec_mem_op,
476 };
477
478 static const struct dm_spi_ops ti_qspi_ops = {
479 .claim_bus = ti_qspi_claim_bus,
480 .release_bus = ti_qspi_release_bus,
481 .xfer = ti_qspi_xfer,
482 .set_speed = ti_qspi_set_speed,
483 .set_mode = ti_qspi_set_mode,
484 .mem_ops = &ti_qspi_mem_ops,
485 };
486
487 static const struct udevice_id ti_qspi_ids[] = {
488 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
489 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
490 { }
491 };
492
493 U_BOOT_DRIVER(ti_qspi) = {
494 .name = "ti_qspi",
495 .id = UCLASS_SPI,
496 .of_match = ti_qspi_ids,
497 .ops = &ti_qspi_ops,
498 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
499 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
500 .probe = ti_qspi_probe,
501 };
502