1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
5 *
6 * Xilinx Zynq PS SPI controller driver (master mode only)
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <time.h>
14 #include <asm/io.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
19 #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
20 #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
21 #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
22 #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
23 #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
24 #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
25 #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
26 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
27 #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
28 #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
29 #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
30
31 #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
32 #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
33 #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
34
35 #define ZYNQ_SPI_FIFO_DEPTH 128
36 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
37 #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
38 #endif
39
40 /* zynq spi register set */
41 struct zynq_spi_regs {
42 u32 cr; /* 0x00 */
43 u32 isr; /* 0x04 */
44 u32 ier; /* 0x08 */
45 u32 idr; /* 0x0C */
46 u32 imr; /* 0x10 */
47 u32 enr; /* 0x14 */
48 u32 dr; /* 0x18 */
49 u32 txdr; /* 0x1C */
50 u32 rxdr; /* 0x20 */
51 };
52
53
54 /* zynq spi platform data */
55 struct zynq_spi_platdata {
56 struct zynq_spi_regs *regs;
57 u32 frequency; /* input frequency */
58 u32 speed_hz;
59 uint deactivate_delay_us; /* Delay to wait after deactivate */
60 uint activate_delay_us; /* Delay to wait after activate */
61 };
62
63 /* zynq spi priv */
64 struct zynq_spi_priv {
65 struct zynq_spi_regs *regs;
66 u8 cs;
67 u8 mode;
68 ulong last_transaction_us; /* Time of last transaction end */
69 u8 fifo_depth;
70 u32 freq; /* required frequency */
71 };
72
zynq_spi_ofdata_to_platdata(struct udevice * bus)73 static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
74 {
75 struct zynq_spi_platdata *plat = bus->platdata;
76 const void *blob = gd->fdt_blob;
77 int node = dev_of_offset(bus);
78
79 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
80
81 /* FIXME: Use 250MHz as a suitable default */
82 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
83 250000000);
84 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
85 "spi-deactivate-delay", 0);
86 plat->activate_delay_us = fdtdec_get_int(blob, node,
87 "spi-activate-delay", 0);
88 plat->speed_hz = plat->frequency / 2;
89
90 debug("%s: regs=%p max-frequency=%d\n", __func__,
91 plat->regs, plat->frequency);
92
93 return 0;
94 }
95
zynq_spi_init_hw(struct zynq_spi_priv * priv)96 static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
97 {
98 struct zynq_spi_regs *regs = priv->regs;
99 u32 confr;
100
101 /* Disable SPI */
102 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
103 writel(~confr, ®s->enr);
104
105 /* Disable Interrupts */
106 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
107
108 /* Clear RX FIFO */
109 while (readl(®s->isr) &
110 ZYNQ_SPI_IXR_RXNEMPTY_MASK)
111 readl(®s->rxdr);
112
113 /* Clear Interrupts */
114 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr);
115
116 /* Manual slave select and Auto start */
117 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
118 ZYNQ_SPI_CR_MSTREN_MASK;
119 confr &= ~ZYNQ_SPI_CR_MSA_MASK;
120 writel(confr, ®s->cr);
121
122 /* Enable SPI */
123 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
124 }
125
zynq_spi_probe(struct udevice * bus)126 static int zynq_spi_probe(struct udevice *bus)
127 {
128 struct zynq_spi_platdata *plat = dev_get_platdata(bus);
129 struct zynq_spi_priv *priv = dev_get_priv(bus);
130
131 priv->regs = plat->regs;
132 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
133
134 /* init the zynq spi hw */
135 zynq_spi_init_hw(priv);
136
137 return 0;
138 }
139
spi_cs_activate(struct udevice * dev)140 static void spi_cs_activate(struct udevice *dev)
141 {
142 struct udevice *bus = dev->parent;
143 struct zynq_spi_platdata *plat = bus->platdata;
144 struct zynq_spi_priv *priv = dev_get_priv(bus);
145 struct zynq_spi_regs *regs = priv->regs;
146 u32 cr;
147
148 /* If it's too soon to do another transaction, wait */
149 if (plat->deactivate_delay_us && priv->last_transaction_us) {
150 ulong delay_us; /* The delay completed so far */
151 delay_us = timer_get_us() - priv->last_transaction_us;
152 if (delay_us < plat->deactivate_delay_us)
153 udelay(plat->deactivate_delay_us - delay_us);
154 }
155
156 clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
157 cr = readl(®s->cr);
158 /*
159 * CS cal logic: CS[13:10]
160 * xxx0 - cs0
161 * xx01 - cs1
162 * x011 - cs2
163 */
164 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
165 writel(cr, ®s->cr);
166
167 if (plat->activate_delay_us)
168 udelay(plat->activate_delay_us);
169 }
170
spi_cs_deactivate(struct udevice * dev)171 static void spi_cs_deactivate(struct udevice *dev)
172 {
173 struct udevice *bus = dev->parent;
174 struct zynq_spi_platdata *plat = bus->platdata;
175 struct zynq_spi_priv *priv = dev_get_priv(bus);
176 struct zynq_spi_regs *regs = priv->regs;
177
178 setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
179
180 /* Remember time of this transaction so we can honour the bus delay */
181 if (plat->deactivate_delay_us)
182 priv->last_transaction_us = timer_get_us();
183 }
184
zynq_spi_claim_bus(struct udevice * dev)185 static int zynq_spi_claim_bus(struct udevice *dev)
186 {
187 struct udevice *bus = dev->parent;
188 struct zynq_spi_priv *priv = dev_get_priv(bus);
189 struct zynq_spi_regs *regs = priv->regs;
190
191 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
192
193 return 0;
194 }
195
zynq_spi_release_bus(struct udevice * dev)196 static int zynq_spi_release_bus(struct udevice *dev)
197 {
198 struct udevice *bus = dev->parent;
199 struct zynq_spi_priv *priv = dev_get_priv(bus);
200 struct zynq_spi_regs *regs = priv->regs;
201 u32 confr;
202
203 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
204 writel(~confr, ®s->enr);
205
206 return 0;
207 }
208
zynq_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)209 static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
210 const void *dout, void *din, unsigned long flags)
211 {
212 struct udevice *bus = dev->parent;
213 struct zynq_spi_priv *priv = dev_get_priv(bus);
214 struct zynq_spi_regs *regs = priv->regs;
215 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
216 u32 len = bitlen / 8;
217 u32 tx_len = len, rx_len = len, tx_tvl;
218 const u8 *tx_buf = dout;
219 u8 *rx_buf = din, buf;
220 u32 ts, status;
221
222 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
223 bus->seq, slave_plat->cs, bitlen, len, flags);
224
225 if (bitlen % 8) {
226 debug("spi_xfer: Non byte aligned SPI transfer\n");
227 return -1;
228 }
229
230 priv->cs = slave_plat->cs;
231 if (flags & SPI_XFER_BEGIN)
232 spi_cs_activate(dev);
233
234 while (rx_len > 0) {
235 /* Write the data into TX FIFO - tx threshold is fifo_depth */
236 tx_tvl = 0;
237 while ((tx_tvl < priv->fifo_depth) && tx_len) {
238 if (tx_buf)
239 buf = *tx_buf++;
240 else
241 buf = 0;
242 writel(buf, ®s->txdr);
243 tx_len--;
244 tx_tvl++;
245 }
246
247 /* Check TX FIFO completion */
248 ts = get_timer(0);
249 status = readl(®s->isr);
250 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
251 if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
252 printf("spi_xfer: Timeout! TX FIFO not full\n");
253 return -1;
254 }
255 status = readl(®s->isr);
256 }
257
258 /* Read the data from RX FIFO */
259 status = readl(®s->isr);
260 while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
261 buf = readl(®s->rxdr);
262 if (rx_buf)
263 *rx_buf++ = buf;
264 status = readl(®s->isr);
265 rx_len--;
266 }
267 }
268
269 if (flags & SPI_XFER_END)
270 spi_cs_deactivate(dev);
271
272 return 0;
273 }
274
zynq_spi_set_speed(struct udevice * bus,uint speed)275 static int zynq_spi_set_speed(struct udevice *bus, uint speed)
276 {
277 struct zynq_spi_platdata *plat = bus->platdata;
278 struct zynq_spi_priv *priv = dev_get_priv(bus);
279 struct zynq_spi_regs *regs = priv->regs;
280 uint32_t confr;
281 u8 baud_rate_val = 0;
282
283 if (speed > plat->frequency)
284 speed = plat->frequency;
285
286 /* Set the clock frequency */
287 confr = readl(®s->cr);
288 if (speed == 0) {
289 /* Set baudrate x8, if the freq is 0 */
290 baud_rate_val = 0x2;
291 } else if (plat->speed_hz != speed) {
292 while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
293 ((plat->frequency /
294 (2 << baud_rate_val)) > speed))
295 baud_rate_val++;
296 plat->speed_hz = speed / (2 << baud_rate_val);
297 }
298 confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
299 confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
300
301 writel(confr, ®s->cr);
302 priv->freq = speed;
303
304 debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
305 priv->regs, priv->freq);
306
307 return 0;
308 }
309
zynq_spi_set_mode(struct udevice * bus,uint mode)310 static int zynq_spi_set_mode(struct udevice *bus, uint mode)
311 {
312 struct zynq_spi_priv *priv = dev_get_priv(bus);
313 struct zynq_spi_regs *regs = priv->regs;
314 uint32_t confr;
315
316 /* Set the SPI Clock phase and polarities */
317 confr = readl(®s->cr);
318 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
319
320 if (mode & SPI_CPHA)
321 confr |= ZYNQ_SPI_CR_CPHA_MASK;
322 if (mode & SPI_CPOL)
323 confr |= ZYNQ_SPI_CR_CPOL_MASK;
324
325 writel(confr, ®s->cr);
326 priv->mode = mode;
327
328 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
329
330 return 0;
331 }
332
333 static const struct dm_spi_ops zynq_spi_ops = {
334 .claim_bus = zynq_spi_claim_bus,
335 .release_bus = zynq_spi_release_bus,
336 .xfer = zynq_spi_xfer,
337 .set_speed = zynq_spi_set_speed,
338 .set_mode = zynq_spi_set_mode,
339 };
340
341 static const struct udevice_id zynq_spi_ids[] = {
342 { .compatible = "xlnx,zynq-spi-r1p6" },
343 { .compatible = "cdns,spi-r1p6" },
344 { }
345 };
346
347 U_BOOT_DRIVER(zynq_spi) = {
348 .name = "zynq_spi",
349 .id = UCLASS_SPI,
350 .of_match = zynq_spi_ids,
351 .ops = &zynq_spi_ops,
352 .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
353 .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
354 .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
355 .probe = zynq_spi_probe,
356 };
357