1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <usb.h>
9 #include <errno.h>
10 #include <wait_bit.h>
11 #include <linux/compiler.h>
12 #include <usb/ehci-ci.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sys_proto.h>
18 #include <dm.h>
19 #include <asm/mach-types.h>
20 #include <power/regulator.h>
21 #include <linux/usb/otg.h>
22
23 #include "ehci.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define USB_OTGREGS_OFFSET 0x000
28 #define USB_H1REGS_OFFSET 0x200
29 #define USB_H2REGS_OFFSET 0x400
30 #define USB_H3REGS_OFFSET 0x600
31 #define USB_OTHERREGS_OFFSET 0x800
32
33 #define USB_H1_CTRL_OFFSET 0x04
34
35 #define USBPHY_CTRL 0x00000030
36 #define USBPHY_CTRL_SET 0x00000034
37 #define USBPHY_CTRL_CLR 0x00000038
38 #define USBPHY_CTRL_TOG 0x0000003c
39
40 #define USBPHY_PWD 0x00000000
41 #define USBPHY_CTRL_SFTRST 0x80000000
42 #define USBPHY_CTRL_CLKGATE 0x40000000
43 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
44 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
45 #define USBPHY_CTRL_OTG_ID 0x08000000
46
47 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
48 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
49
50 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
51 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
52 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
53 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
54
55 #define USBNC_OFFSET 0x200
56 #define USBNC_PHY_STATUS_OFFSET 0x23C
57 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
58 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
59 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
60 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
61 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
62
63 /* USBCMD */
64 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
65 #define UCMD_RESET (1 << 1) /* controller reset */
66
67 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
68 static const unsigned phy_bases[] = {
69 USB_PHY0_BASE_ADDR,
70 #if defined(USB_PHY1_BASE_ADDR)
71 USB_PHY1_BASE_ADDR,
72 #endif
73 };
74
usb_internal_phy_clock_gate(int index,int on)75 static void usb_internal_phy_clock_gate(int index, int on)
76 {
77 void __iomem *phy_reg;
78
79 if (index >= ARRAY_SIZE(phy_bases))
80 return;
81
82 phy_reg = (void __iomem *)phy_bases[index];
83 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
84 writel(USBPHY_CTRL_CLKGATE, phy_reg);
85 }
86
usb_power_config(int index)87 static void usb_power_config(int index)
88 {
89 #if defined(CONFIG_MX7ULP)
90 struct usbphy_regs __iomem *usbphy =
91 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
92
93 if (index > 0)
94 return;
95
96 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
97 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
98 &usbphy->usb1_chrg_detect);
99
100 scg_enable_usb_pll(true);
101
102 #else
103 struct anatop_regs __iomem *anatop =
104 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
105 void __iomem *chrg_detect;
106 void __iomem *pll_480_ctrl_clr;
107 void __iomem *pll_480_ctrl_set;
108
109 switch (index) {
110 case 0:
111 chrg_detect = &anatop->usb1_chrg_detect;
112 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
113 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
114 break;
115 case 1:
116 chrg_detect = &anatop->usb2_chrg_detect;
117 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
118 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
119 break;
120 default:
121 return;
122 }
123 /*
124 * Some phy and power's special controls
125 * 1. The external charger detector needs to be disabled
126 * or the signal at DP will be poor
127 * 2. The PLL's power and output to usb
128 * is totally controlled by IC, so the Software only needs
129 * to enable them at initializtion.
130 */
131 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
132 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
133 chrg_detect);
134
135 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
136 pll_480_ctrl_clr);
137
138 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
139 ANADIG_USB2_PLL_480_CTRL_POWER |
140 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
141 pll_480_ctrl_set);
142
143 #endif
144 }
145
146 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(int index,struct usb_ehci * ehci)147 static int usb_phy_enable(int index, struct usb_ehci *ehci)
148 {
149 void __iomem *phy_reg;
150 void __iomem *phy_ctrl;
151 void __iomem *usb_cmd;
152 int ret;
153
154 if (index >= ARRAY_SIZE(phy_bases))
155 return 0;
156
157 phy_reg = (void __iomem *)phy_bases[index];
158 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
159 usb_cmd = (void __iomem *)&ehci->usbcmd;
160
161 /* Stop then Reset */
162 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
163 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
164 if (ret)
165 return ret;
166
167 setbits_le32(usb_cmd, UCMD_RESET);
168 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
169 if (ret)
170 return ret;
171
172 /* Reset USBPHY module */
173 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
174 udelay(10);
175
176 /* Remove CLKGATE and SFTRST */
177 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
178 udelay(10);
179
180 /* Power up the PHY */
181 writel(0, phy_reg + USBPHY_PWD);
182 /* enable FS/LS device */
183 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
184 USBPHY_CTRL_ENUTMILEVEL3);
185
186 return 0;
187 }
188
usb_phy_mode(int port)189 int usb_phy_mode(int port)
190 {
191 void __iomem *phy_reg;
192 void __iomem *phy_ctrl;
193 u32 val;
194
195 phy_reg = (void __iomem *)phy_bases[port];
196 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
197
198 val = readl(phy_ctrl);
199
200 if (val & USBPHY_CTRL_OTG_ID)
201 return USB_INIT_DEVICE;
202 else
203 return USB_INIT_HOST;
204 }
205
206 #if defined(CONFIG_MX7ULP)
207 struct usbnc_regs {
208 u32 ctrl1;
209 u32 ctrl2;
210 u32 reserve0[2];
211 u32 hsic_ctrl;
212 };
213 #else
214 /* Base address for this IP block is 0x02184800 */
215 struct usbnc_regs {
216 u32 ctrl[4]; /* otg/host1-3 */
217 u32 uh2_hsic_ctrl;
218 u32 uh3_hsic_ctrl;
219 u32 otg_phy_ctrl_0;
220 u32 uh1_phy_ctrl_0;
221 };
222 #endif
223
224 #elif defined(CONFIG_MX7)
225 struct usbnc_regs {
226 u32 ctrl1;
227 u32 ctrl2;
228 u32 reserve1[10];
229 u32 phy_cfg1;
230 u32 phy_cfg2;
231 u32 reserve2;
232 u32 phy_status;
233 u32 reserve3[4];
234 u32 adp_cfg1;
235 u32 adp_cfg2;
236 u32 adp_status;
237 };
238
usb_power_config(int index)239 static void usb_power_config(int index)
240 {
241 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
242 (0x10000 * index) + USBNC_OFFSET);
243 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
244
245 /*
246 * Clear the ACAENB to enable usb_otg_id detection,
247 * otherwise it is the ACA detection enabled.
248 */
249 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
250 }
251
usb_phy_mode(int port)252 int usb_phy_mode(int port)
253 {
254 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
255 (0x10000 * port) + USBNC_OFFSET);
256 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
257 u32 val;
258
259 val = readl(status);
260
261 if (val & USBNC_PHYSTATUS_ID_DIG)
262 return USB_INIT_DEVICE;
263 else
264 return USB_INIT_HOST;
265 }
266 #endif
267
usb_oc_config(int index)268 static void usb_oc_config(int index)
269 {
270 #if defined(CONFIG_MX6)
271 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
272 USB_OTHERREGS_OFFSET);
273 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
274 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
275 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
276 (0x10000 * index) + USBNC_OFFSET);
277 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
278 #endif
279
280 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
281 /* mx6qarm2 seems to required a different setting*/
282 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
283 #else
284 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
285 #endif
286
287 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
288
289 /* Set power polarity to high active */
290 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
291 setbits_le32(ctrl, UCTRL_PWR_POL);
292 #else
293 clrbits_le32(ctrl, UCTRL_PWR_POL);
294 #endif
295 }
296
297 /**
298 * board_usb_phy_mode - override usb phy mode
299 * @port: usb host/otg port
300 *
301 * Target board specific, override usb_phy_mode.
302 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
303 * left disconnected in this case usb_phy_mode will not be able to identify
304 * the phy mode that usb port is used.
305 * Machine file overrides board_usb_phy_mode.
306 *
307 * Return: USB_INIT_DEVICE or USB_INIT_HOST
308 */
board_usb_phy_mode(int port)309 int __weak board_usb_phy_mode(int port)
310 {
311 return usb_phy_mode(port);
312 }
313
314 /**
315 * board_ehci_hcd_init - set usb vbus voltage
316 * @port: usb otg port
317 *
318 * Target board specific, setup iomux pad to setup supply vbus voltage
319 * for usb otg port. Machine board file overrides board_ehci_hcd_init
320 *
321 * Return: 0 Success
322 */
board_ehci_hcd_init(int port)323 int __weak board_ehci_hcd_init(int port)
324 {
325 return 0;
326 }
327
328 /**
329 * board_ehci_power - enables/disables usb vbus voltage
330 * @port: usb otg port
331 * @on: on/off vbus voltage
332 *
333 * Enables/disables supply vbus voltage for usb otg port.
334 * Machine board file overrides board_ehci_power
335 *
336 * Return: 0 Success
337 */
board_ehci_power(int port,int on)338 int __weak board_ehci_power(int port, int on)
339 {
340 return 0;
341 }
342
ehci_mx6_common_init(struct usb_ehci * ehci,int index)343 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
344 {
345 int ret;
346
347 enable_usboh3_clk(1);
348 mdelay(1);
349
350 /* Do board specific initialization */
351 ret = board_ehci_hcd_init(index);
352 if (ret)
353 return ret;
354
355 usb_power_config(index);
356 usb_oc_config(index);
357
358 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
359 usb_internal_phy_clock_gate(index, 1);
360 usb_phy_enable(index, ehci);
361 #endif
362
363 return 0;
364 }
365
366 #if !CONFIG_IS_ENABLED(DM_USB)
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)367 int ehci_hcd_init(int index, enum usb_init_type init,
368 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
369 {
370 enum usb_init_type type;
371 #if defined(CONFIG_MX6)
372 u32 controller_spacing = 0x200;
373 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
374 u32 controller_spacing = 0x10000;
375 #endif
376 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
377 (controller_spacing * index));
378 int ret;
379
380 if (index > 3)
381 return -EINVAL;
382
383 ret = ehci_mx6_common_init(ehci, index);
384 if (ret)
385 return ret;
386
387 type = board_usb_phy_mode(index);
388
389 if (hccr && hcor) {
390 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
391 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
392 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
393 }
394
395 if ((type == init) || (type == USB_INIT_DEVICE))
396 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
397 if (type != init)
398 return -ENODEV;
399 if (type == USB_INIT_DEVICE)
400 return 0;
401
402 setbits_le32(&ehci->usbmode, CM_HOST);
403 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
404 setbits_le32(&ehci->portsc, USB_EN);
405
406 mdelay(10);
407
408 return 0;
409 }
410
ehci_hcd_stop(int index)411 int ehci_hcd_stop(int index)
412 {
413 return 0;
414 }
415 #else
416 struct ehci_mx6_priv_data {
417 struct ehci_ctrl ctrl;
418 struct usb_ehci *ehci;
419 struct udevice *vbus_supply;
420 enum usb_init_type init_type;
421 int portnr;
422 };
423
mx6_init_after_reset(struct ehci_ctrl * dev)424 static int mx6_init_after_reset(struct ehci_ctrl *dev)
425 {
426 struct ehci_mx6_priv_data *priv = dev->priv;
427 enum usb_init_type type = priv->init_type;
428 struct usb_ehci *ehci = priv->ehci;
429 int ret;
430
431 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
432 if (ret)
433 return ret;
434
435 #if CONFIG_IS_ENABLED(DM_REGULATOR)
436 if (priv->vbus_supply) {
437 ret = regulator_set_enable(priv->vbus_supply,
438 (type == USB_INIT_DEVICE) ?
439 false : true);
440 if (ret) {
441 puts("Error enabling VBUS supply\n");
442 return ret;
443 }
444 }
445 #endif
446
447 if (type == USB_INIT_DEVICE)
448 return 0;
449
450 setbits_le32(&ehci->usbmode, CM_HOST);
451 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
452 setbits_le32(&ehci->portsc, USB_EN);
453
454 mdelay(10);
455
456 return 0;
457 }
458
459 static const struct ehci_ops mx6_ehci_ops = {
460 .init_after_reset = mx6_init_after_reset
461 };
462
ehci_usb_phy_mode(struct udevice * dev)463 static int ehci_usb_phy_mode(struct udevice *dev)
464 {
465 struct usb_platdata *plat = dev_get_platdata(dev);
466 void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
467 void *__iomem phy_ctrl, *__iomem phy_status;
468 const void *blob = gd->fdt_blob;
469 int offset = dev_of_offset(dev), phy_off;
470 u32 val;
471
472 /*
473 * About fsl,usbphy, Refer to
474 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
475 */
476 if (is_mx6() || is_mx7ulp()) {
477 phy_off = fdtdec_lookup_phandle(blob,
478 offset,
479 "fsl,usbphy");
480 if (phy_off < 0)
481 return -EINVAL;
482
483 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
484 "reg");
485 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
486 return -EINVAL;
487
488 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
489 val = readl(phy_ctrl);
490
491 if (val & USBPHY_CTRL_OTG_ID)
492 plat->init_type = USB_INIT_DEVICE;
493 else
494 plat->init_type = USB_INIT_HOST;
495 } else if (is_mx7()) {
496 phy_status = (void __iomem *)(addr +
497 USBNC_PHY_STATUS_OFFSET);
498 val = readl(phy_status);
499
500 if (val & USBNC_PHYSTATUS_ID_DIG)
501 plat->init_type = USB_INIT_DEVICE;
502 else
503 plat->init_type = USB_INIT_HOST;
504 } else {
505 return -EINVAL;
506 }
507
508 return 0;
509 }
510
ehci_usb_ofdata_to_platdata(struct udevice * dev)511 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
512 {
513 struct usb_platdata *plat = dev_get_platdata(dev);
514 enum usb_dr_mode dr_mode;
515
516 dr_mode = usb_get_dr_mode(dev_of_offset(dev));
517
518 switch (dr_mode) {
519 case USB_DR_MODE_HOST:
520 plat->init_type = USB_INIT_HOST;
521 break;
522 case USB_DR_MODE_PERIPHERAL:
523 plat->init_type = USB_INIT_DEVICE;
524 break;
525 case USB_DR_MODE_OTG:
526 case USB_DR_MODE_UNKNOWN:
527 return ehci_usb_phy_mode(dev);
528 };
529
530 return 0;
531 }
532
ehci_usb_bind(struct udevice * dev)533 static int ehci_usb_bind(struct udevice *dev)
534 {
535 /*
536 * TODO:
537 * This driver is only partly converted to DT probing and still uses
538 * a tremendous amount of hard-coded addresses. To make things worse,
539 * the driver depends on specific sequential indexing of controllers,
540 * from which it derives offsets in the PHY and ANATOP register sets.
541 *
542 * Here we attempt to calculate these indexes from DT information as
543 * well as we can. The USB controllers on all existing iMX6 SoCs
544 * are placed next to each other, at addresses incremented by 0x200,
545 * and iMX7 their addresses are shifted by 0x10000.
546 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
547 * iMX7) offset from the first controller address.
548 *
549 * However, to complete conversion of this driver to DT probing, the
550 * following has to be done:
551 * - DM clock framework support for iMX must be implemented
552 * - usb_power_config() has to be converted to clock framework
553 * -> Thus, the ad-hoc "index" variable goes away.
554 * - USB PHY handling has to be factored out into separate driver
555 * -> Thus, the ad-hoc "index" variable goes away from the PHY
556 * code, the PHY driver must parse it's address from DT. This
557 * USB driver must find the PHY driver via DT phandle.
558 * -> usb_power_config() shall be moved to PHY driver
559 * With these changes in place, the ad-hoc indexing goes away and
560 * the driver is fully converted to DT probing.
561 */
562 u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
563 fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
564
565 dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
566
567 return 0;
568 }
569
ehci_usb_probe(struct udevice * dev)570 static int ehci_usb_probe(struct udevice *dev)
571 {
572 struct usb_platdata *plat = dev_get_platdata(dev);
573 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
574 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
575 enum usb_init_type type = plat->init_type;
576 struct ehci_hccr *hccr;
577 struct ehci_hcor *hcor;
578 int ret;
579
580 priv->ehci = ehci;
581 priv->portnr = dev->seq;
582 priv->init_type = type;
583
584 #if CONFIG_IS_ENABLED(DM_REGULATOR)
585 ret = device_get_supply_regulator(dev, "vbus-supply",
586 &priv->vbus_supply);
587 if (ret)
588 debug("%s: No vbus supply\n", dev->name);
589 #endif
590 ret = ehci_mx6_common_init(ehci, priv->portnr);
591 if (ret)
592 return ret;
593
594 #if CONFIG_IS_ENABLED(DM_REGULATOR)
595 if (priv->vbus_supply) {
596 ret = regulator_set_enable(priv->vbus_supply,
597 (type == USB_INIT_DEVICE) ?
598 false : true);
599 if (ret) {
600 puts("Error enabling VBUS supply\n");
601 return ret;
602 }
603 }
604 #endif
605
606 if (priv->init_type == USB_INIT_HOST) {
607 setbits_le32(&ehci->usbmode, CM_HOST);
608 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
609 setbits_le32(&ehci->portsc, USB_EN);
610 }
611
612 mdelay(10);
613
614 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
615 hcor = (struct ehci_hcor *)((uint32_t)hccr +
616 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
617
618 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
619 }
620
621 static const struct udevice_id mx6_usb_ids[] = {
622 { .compatible = "fsl,imx27-usb" },
623 { }
624 };
625
626 U_BOOT_DRIVER(usb_mx6) = {
627 .name = "ehci_mx6",
628 .id = UCLASS_USB,
629 .of_match = mx6_usb_ids,
630 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
631 .bind = ehci_usb_bind,
632 .probe = ehci_usb_probe,
633 .remove = ehci_deregister,
634 .ops = &ehci_usb_ops,
635 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
636 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
637 .flags = DM_FLAG_ALLOC_PRIV_DMA,
638 };
639 #endif
640