1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8
9 #include "../gadget/dwc2_udc_otg_priv.h"
10
11 DECLARE_GLOBAL_DATA_PTR;
12
13 #define BIT_WRITEABLE_SHIFT 16
14
15 struct usb2phy_reg {
16 unsigned int offset;
17 unsigned int bitend;
18 unsigned int bitstart;
19 unsigned int disable;
20 unsigned int enable;
21 };
22
23 /**
24 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
25 * @port_reset: usb otg per-port reset register
26 * @soft_con: software control usb otg register
27 * @suspend: phy suspend register
28 */
29 struct rockchip_usb2_phy_cfg {
30 struct usb2phy_reg port_reset;
31 struct usb2phy_reg soft_con;
32 struct usb2phy_reg suspend;
33 };
34
35 struct rockchip_usb2_phy_dt_id {
36 char compatible[128];
37 const void *data;
38 };
39
40 static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
41 .port_reset = {0x00, 12, 12, 0, 1},
42 .soft_con = {0x08, 2, 2, 0, 1},
43 .suspend = {0x0c, 5, 0, 0x01, 0x2A},
44 };
45
46 static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
47 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
48 {}
49 };
50
property_enable(struct dwc2_plat_otg_data * pdata,const struct usb2phy_reg * reg,bool en)51 static void property_enable(struct dwc2_plat_otg_data *pdata,
52 const struct usb2phy_reg *reg, bool en)
53 {
54 unsigned int val, mask, tmp;
55
56 tmp = en ? reg->enable : reg->disable;
57 mask = GENMASK(reg->bitend, reg->bitstart);
58 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
59
60 writel(val, pdata->regs_phy + reg->offset);
61 }
62
63
otg_phy_init(struct dwc2_udc * dev)64 void otg_phy_init(struct dwc2_udc *dev)
65 {
66 struct dwc2_plat_otg_data *pdata = dev->pdata;
67 struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
68 struct rockchip_usb2_phy_dt_id *of_id;
69 int i;
70
71 for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
72 of_id = &rockchip_usb2_phy_dt_ids[i];
73 if (ofnode_device_is_compatible(pdata->phy_of_node,
74 of_id->compatible)){
75 phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
76 break;
77 }
78 }
79 if (!phy_cfg) {
80 debug("Can't find device platform data\n");
81
82 hang();
83 return;
84 }
85 pdata->priv = phy_cfg;
86 /* disable software control */
87 property_enable(pdata, &phy_cfg->soft_con, false);
88
89 /* reset otg port */
90 property_enable(pdata, &phy_cfg->port_reset, true);
91 mdelay(1);
92 property_enable(pdata, &phy_cfg->port_reset, false);
93 udelay(1);
94 }
95
otg_phy_off(struct dwc2_udc * dev)96 void otg_phy_off(struct dwc2_udc *dev)
97 {
98 struct dwc2_plat_otg_data *pdata = dev->pdata;
99 struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
100
101 /* enable software control */
102 property_enable(pdata, &phy_cfg->soft_con, true);
103 /* enter suspend */
104 property_enable(pdata, &phy_cfg->suspend, true);
105 }
106