1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
6 *
7 * This MIPI DSI controller driver is based on the Linux Kernel driver from
8 * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <dsi_host.h>
15 #include <mipi_dsi.h>
16 #include <panel.h>
17 #include <reset.h>
18 #include <video.h>
19 #include <video_bridge.h>
20 #include <asm/io.h>
21 #include <asm/arch/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dm/lists.h>
24 #include <linux/iopoll.h>
25 #include <power/regulator.h>
26
27 #define HWVER_130 0x31333000 /* IP version 1.30 */
28 #define HWVER_131 0x31333100 /* IP version 1.31 */
29
30 /* DSI digital registers & bit definitions */
31 #define DSI_VERSION 0x00
32 #define VERSION GENMASK(31, 8)
33
34 /*
35 * DSI wrapper registers & bit definitions
36 * Note: registers are named as in the Reference Manual
37 */
38 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
39 #define WCFGR_DSIM BIT(0) /* DSI Mode */
40 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
41
42 #define DSI_WCR 0x0404 /* Wrapper Control Reg */
43 #define WCR_DSIEN BIT(3) /* DSI ENable */
44
45 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
46 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
47 #define WISR_RRS BIT(12) /* Regulator Ready Status */
48
49 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
50 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
51 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
52
53 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
54 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
55 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
56 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
57 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
58 #define WRPCR_REGEN BIT(24) /* REGulator ENable */
59 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
60 #define IDF_MIN 1
61 #define IDF_MAX 7
62 #define NDIV_MIN 10
63 #define NDIV_MAX 125
64 #define ODF_MIN 1
65 #define ODF_MAX 8
66
67 /* dsi color format coding according to the datasheet */
68 enum dsi_color {
69 DSI_RGB565_CONF1,
70 DSI_RGB565_CONF2,
71 DSI_RGB565_CONF3,
72 DSI_RGB666_CONF1,
73 DSI_RGB666_CONF2,
74 DSI_RGB888,
75 };
76
77 #define LANE_MIN_KBPS 31250
78 #define LANE_MAX_KBPS 500000
79
80 /* Timeout for regulator on/off, pll lock/unlock & fifo empty */
81 #define TIMEOUT_US 200000
82
83 struct stm32_dsi_priv {
84 struct mipi_dsi_device device;
85 void __iomem *base;
86 struct udevice *panel;
87 u32 pllref_clk;
88 u32 hw_version;
89 int lane_min_kbps;
90 int lane_max_kbps;
91 struct udevice *vdd_reg;
92 struct udevice *dsi_host;
93 };
94
dsi_write(struct stm32_dsi_priv * dsi,u32 reg,u32 val)95 static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
96 {
97 writel(val, dsi->base + reg);
98 }
99
dsi_read(struct stm32_dsi_priv * dsi,u32 reg)100 static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
101 {
102 return readl(dsi->base + reg);
103 }
104
dsi_set(struct stm32_dsi_priv * dsi,u32 reg,u32 mask)105 static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
106 {
107 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
108 }
109
dsi_clear(struct stm32_dsi_priv * dsi,u32 reg,u32 mask)110 static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
111 {
112 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
113 }
114
dsi_update_bits(struct stm32_dsi_priv * dsi,u32 reg,u32 mask,u32 val)115 static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
116 u32 mask, u32 val)
117 {
118 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
119 }
120
dsi_color_from_mipi(u32 fmt)121 static enum dsi_color dsi_color_from_mipi(u32 fmt)
122 {
123 switch (fmt) {
124 case MIPI_DSI_FMT_RGB888:
125 return DSI_RGB888;
126 case MIPI_DSI_FMT_RGB666:
127 return DSI_RGB666_CONF2;
128 case MIPI_DSI_FMT_RGB666_PACKED:
129 return DSI_RGB666_CONF1;
130 case MIPI_DSI_FMT_RGB565:
131 return DSI_RGB565_CONF1;
132 default:
133 pr_err("MIPI color invalid, so we use rgb888\n");
134 }
135 return DSI_RGB888;
136 }
137
dsi_pll_get_clkout_khz(int clkin_khz,int idf,int ndiv,int odf)138 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
139 {
140 int divisor = idf * odf;
141
142 /* prevent from division by 0 */
143 if (!divisor)
144 return 0;
145
146 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
147 }
148
dsi_pll_get_params(struct stm32_dsi_priv * dsi,int clkin_khz,int clkout_khz,int * idf,int * ndiv,int * odf)149 static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
150 int clkin_khz, int clkout_khz,
151 int *idf, int *ndiv, int *odf)
152 {
153 int i, o, n, n_min, n_max;
154 int fvco_min, fvco_max, delta, best_delta; /* all in khz */
155
156 /* Early checks preventing division by 0 & odd results */
157 if (clkin_khz <= 0 || clkout_khz <= 0)
158 return -EINVAL;
159
160 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
161 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
162
163 best_delta = 1000000; /* big started value (1000000khz) */
164
165 for (i = IDF_MIN; i <= IDF_MAX; i++) {
166 /* Compute ndiv range according to Fvco */
167 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
168 n_max = (fvco_max * i) / (2 * clkin_khz);
169
170 /* No need to continue idf loop if we reach ndiv max */
171 if (n_min >= NDIV_MAX)
172 break;
173
174 /* Clamp ndiv to valid values */
175 if (n_min < NDIV_MIN)
176 n_min = NDIV_MIN;
177 if (n_max > NDIV_MAX)
178 n_max = NDIV_MAX;
179
180 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
181 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
182 /* Check ndiv according to vco range */
183 if (n < n_min || n > n_max)
184 continue;
185 /* Check if new delta is better & saves parameters */
186 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
187 clkout_khz;
188 if (delta < 0)
189 delta = -delta;
190 if (delta < best_delta) {
191 *idf = i;
192 *ndiv = n;
193 *odf = o;
194 best_delta = delta;
195 }
196 /* fast return in case of "perfect result" */
197 if (!delta)
198 return 0;
199 }
200 }
201
202 return 0;
203 }
204
dsi_phy_init(void * priv_data)205 static int dsi_phy_init(void *priv_data)
206 {
207 struct mipi_dsi_device *device = priv_data;
208 struct udevice *dev = device->dev;
209 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
210 u32 val;
211 int ret;
212
213 debug("Initialize DSI physical layer\n");
214
215 /* Enable the regulator */
216 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
217 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
218 TIMEOUT_US);
219 if (ret) {
220 debug("!TIMEOUT! waiting REGU\n");
221 return ret;
222 }
223
224 /* Enable the DSI PLL & wait for its lock */
225 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
226 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
227 TIMEOUT_US);
228 if (ret) {
229 debug("!TIMEOUT! waiting PLL\n");
230 return ret;
231 }
232
233 return 0;
234 }
235
dsi_phy_post_set_mode(void * priv_data,unsigned long mode_flags)236 static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
237 {
238 struct mipi_dsi_device *device = priv_data;
239 struct udevice *dev = device->dev;
240 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
241
242 debug("Set mode %p enable %ld\n", dsi,
243 mode_flags & MIPI_DSI_MODE_VIDEO);
244
245 if (!dsi)
246 return;
247
248 /*
249 * DSI wrapper must be enabled in video mode & disabled in command mode.
250 * If wrapper is enabled in command mode, the display controller
251 * register access will hang.
252 */
253
254 if (mode_flags & MIPI_DSI_MODE_VIDEO)
255 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
256 else
257 dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
258 }
259
dsi_get_lane_mbps(void * priv_data,struct display_timing * timings,u32 lanes,u32 format,unsigned int * lane_mbps)260 static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
261 u32 lanes, u32 format, unsigned int *lane_mbps)
262 {
263 struct mipi_dsi_device *device = priv_data;
264 struct udevice *dev = device->dev;
265 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
266 int idf, ndiv, odf, pll_in_khz, pll_out_khz;
267 int ret, bpp;
268 u32 val;
269
270 /* Update lane capabilities according to hw version */
271 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
272 dsi->lane_min_kbps = LANE_MIN_KBPS;
273 dsi->lane_max_kbps = LANE_MAX_KBPS;
274 if (dsi->hw_version == HWVER_131) {
275 dsi->lane_min_kbps *= 2;
276 dsi->lane_max_kbps *= 2;
277 }
278
279 pll_in_khz = dsi->pllref_clk / 1000;
280
281 /* Compute requested pll out */
282 bpp = mipi_dsi_pixel_format_to_bpp(format);
283 pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
284 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
285 pll_out_khz = (pll_out_khz * 12) / 10;
286 if (pll_out_khz > dsi->lane_max_kbps) {
287 pll_out_khz = dsi->lane_max_kbps;
288 dev_warn(dev, "Warning max phy mbps is used\n");
289 }
290 if (pll_out_khz < dsi->lane_min_kbps) {
291 pll_out_khz = dsi->lane_min_kbps;
292 dev_warn(dev, "Warning min phy mbps is used\n");
293 }
294
295 /* Compute best pll parameters */
296 idf = 0;
297 ndiv = 0;
298 odf = 0;
299 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
300 &idf, &ndiv, &odf);
301 if (ret) {
302 dev_err(dev, "Warning dsi_pll_get_params(): bad params\n");
303 return ret;
304 }
305
306 /* Get the adjusted pll out value */
307 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
308
309 /* Set the PLL division factors */
310 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
311 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
312
313 /* Compute uix4 & set the bit period in high-speed mode */
314 val = 4000000 / pll_out_khz;
315 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
316
317 /* Select video mode by resetting DSIM bit */
318 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
319
320 /* Select the color coding */
321 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
322 dsi_color_from_mipi(format) << 1);
323
324 *lane_mbps = pll_out_khz / 1000;
325
326 debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
327 pll_in_khz, pll_out_khz, *lane_mbps);
328
329 return 0;
330 }
331
332 static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
333 .init = dsi_phy_init,
334 .get_lane_mbps = dsi_get_lane_mbps,
335 .post_set_mode = dsi_phy_post_set_mode,
336 };
337
stm32_dsi_attach(struct udevice * dev)338 static int stm32_dsi_attach(struct udevice *dev)
339 {
340 struct stm32_dsi_priv *priv = dev_get_priv(dev);
341 struct mipi_dsi_device *device = &priv->device;
342 struct mipi_dsi_panel_plat *mplat;
343 struct display_timing timings;
344 int ret;
345
346 ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
347 if (ret) {
348 dev_err(dev, "panel device error %d\n", ret);
349 return ret;
350 }
351
352 mplat = dev_get_platdata(priv->panel);
353 mplat->device = &priv->device;
354
355 ret = panel_get_display_timing(priv->panel, &timings);
356 if (ret) {
357 ret = fdtdec_decode_display_timing(gd->fdt_blob,
358 dev_of_offset(priv->panel),
359 0, &timings);
360 if (ret) {
361 dev_err(dev, "decode display timing error %d\n", ret);
362 return ret;
363 }
364 }
365
366 ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
367 if (ret) {
368 dev_err(dev, "No video dsi host detected %d\n", ret);
369 return ret;
370 }
371
372 ret = dsi_host_init(priv->dsi_host, device, &timings, 2,
373 &dsi_stm_phy_ops);
374 if (ret) {
375 dev_err(dev, "failed to initialize mipi dsi host\n");
376 return ret;
377 }
378
379 return 0;
380 }
381
stm32_dsi_set_backlight(struct udevice * dev,int percent)382 static int stm32_dsi_set_backlight(struct udevice *dev, int percent)
383 {
384 struct stm32_dsi_priv *priv = dev_get_priv(dev);
385 int ret;
386
387 ret = panel_enable_backlight(priv->panel);
388 if (ret) {
389 dev_err(dev, "panel %s enable backlight error %d\n",
390 priv->panel->name, ret);
391 return ret;
392 }
393
394 ret = dsi_host_enable(priv->dsi_host);
395 if (ret) {
396 dev_err(dev, "failed to enable mipi dsi host\n");
397 return ret;
398 }
399
400 return 0;
401 }
402
stm32_dsi_bind(struct udevice * dev)403 static int stm32_dsi_bind(struct udevice *dev)
404 {
405 int ret;
406
407 ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost",
408 dev_ofnode(dev), NULL);
409 if (ret)
410 return ret;
411
412 return dm_scan_fdt_dev(dev);
413 }
414
stm32_dsi_probe(struct udevice * dev)415 static int stm32_dsi_probe(struct udevice *dev)
416 {
417 struct stm32_dsi_priv *priv = dev_get_priv(dev);
418 struct mipi_dsi_device *device = &priv->device;
419 struct reset_ctl rst;
420 struct clk clk;
421 int ret;
422
423 device->dev = dev;
424
425 priv->base = (void *)dev_read_addr(dev);
426 if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
427 dev_err(dev, "dsi dt register address error\n");
428 return -EINVAL;
429 }
430
431 if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
432 ret = device_get_supply_regulator(dev, "phy-dsi-supply",
433 &priv->vdd_reg);
434 if (ret && ret != -ENOENT) {
435 dev_err(dev, "Warning: cannot get phy dsi supply\n");
436 return -ENODEV;
437 }
438
439 if (ret != -ENOENT) {
440 ret = regulator_set_enable(priv->vdd_reg, true);
441 if (ret)
442 return ret;
443 }
444 }
445
446 ret = clk_get_by_name(device->dev, "pclk", &clk);
447 if (ret) {
448 dev_err(dev, "peripheral clock get error %d\n", ret);
449 goto err_reg;
450 }
451
452 ret = clk_enable(&clk);
453 if (ret) {
454 dev_err(dev, "peripheral clock enable error %d\n", ret);
455 goto err_reg;
456 }
457
458 ret = clk_get_by_name(dev, "ref", &clk);
459 if (ret) {
460 dev_err(dev, "pll reference clock get error %d\n", ret);
461 goto err_clk;
462 }
463
464 priv->pllref_clk = (unsigned int)clk_get_rate(&clk);
465
466 ret = reset_get_by_index(device->dev, 0, &rst);
467 if (ret) {
468 dev_err(dev, "missing dsi hardware reset\n");
469 goto err_clk;
470 }
471
472 /* Reset */
473 reset_deassert(&rst);
474
475 return 0;
476 err_clk:
477 clk_disable(&clk);
478 err_reg:
479 if (IS_ENABLED(CONFIG_DM_REGULATOR))
480 regulator_set_enable(priv->vdd_reg, false);
481
482 return ret;
483 }
484
485 struct video_bridge_ops stm32_dsi_ops = {
486 .attach = stm32_dsi_attach,
487 .set_backlight = stm32_dsi_set_backlight,
488 };
489
490 static const struct udevice_id stm32_dsi_ids[] = {
491 { .compatible = "st,stm32-dsi"},
492 { }
493 };
494
495 U_BOOT_DRIVER(stm32_dsi) = {
496 .name = "stm32-display-dsi",
497 .id = UCLASS_VIDEO_BRIDGE,
498 .of_match = stm32_dsi_ids,
499 .bind = stm32_dsi_bind,
500 .probe = stm32_dsi_probe,
501 .ops = &stm32_dsi_ops,
502 .priv_auto_alloc_size = sizeof(struct stm32_dsi_priv),
503 };
504