1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * C29XPCIE board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_SPIFLASH 14 #define CONFIG_RAMBOOT_SPIFLASH 15 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 16 #endif 17 18 #ifdef CONFIG_MTD_RAW_NAND 19 #ifdef CONFIG_TPL_BUILD 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_NAND_INIT 22 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 23 #define CONFIG_SPL_COMMON_INIT_DDR 24 #define CONFIG_SPL_MAX_SIZE (128 << 10) 25 #define CONFIG_TPL_TEXT_BASE 0xf8f81000 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 28 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 29 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 30 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 31 #elif defined(CONFIG_SPL_BUILD) 32 #define CONFIG_SPL_INIT_MINIMAL 33 #define CONFIG_SPL_NAND_MINIMAL 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_MAX_SIZE 8192 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 40 #endif 41 #define CONFIG_SPL_PAD_TO 0x20000 42 #define CONFIG_TPL_PAD_TO 0x20000 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 #endif 45 46 #ifndef CONFIG_RESET_VECTOR_ADDRESS 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 48 #endif 49 50 #ifdef CONFIG_TPL_BUILD 51 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 52 #elif defined(CONFIG_SPL_BUILD) 53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 54 #else 55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 56 #endif 57 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #endif 61 62 /* High Level Configuration Options */ 63 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 64 65 #ifdef CONFIG_PCI 66 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_PCI_INDIRECT_BRIDGE 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 /* 72 * PCI Windows 73 * Memory space is mapped 1-1, but I/O space must start from 0. 74 */ 75 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 76 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 77 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 78 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 79 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 80 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 81 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 82 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 83 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 84 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 85 86 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 87 #endif 88 89 #define CONFIG_ENV_OVERWRITE 90 91 #define CONFIG_DDR_CLK_FREQ 100000000 92 #define CONFIG_SYS_CLK_FREQ 66666666 93 94 #define CONFIG_HWCONFIG 95 96 /* 97 * These can be toggled for performance analysis, otherwise use default. 98 */ 99 #define CONFIG_L2_CACHE /* toggle L2 cache */ 100 #define CONFIG_BTB /* toggle branch predition */ 101 102 103 #define CONFIG_ENABLE_36BIT_PHYS 104 105 #define CONFIG_ADDR_MAP 1 106 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 107 108 #define CONFIG_SYS_MEMTEST_START 0x00200000 109 #define CONFIG_SYS_MEMTEST_END 0x00400000 110 111 /* DDR Setup */ 112 #define CONFIG_DDR_SPD 113 #define CONFIG_SYS_SPD_BUS_NUM 0 114 #define SPD_EEPROM_ADDRESS 0x50 115 #define CONFIG_SYS_DDR_RAW_TIMING 116 117 /* DDR ECC Setup*/ 118 #define CONFIG_DDR_ECC 119 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 121 122 #define CONFIG_SYS_SDRAM_SIZE 512 123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 125 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 128 129 #define CONFIG_SYS_CCSRBAR 0xffe00000 130 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 131 132 /* Platform SRAM setting */ 133 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 134 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 135 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 136 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 137 138 /* 139 * IFC Definitions 140 */ 141 /* NOR Flash on IFC */ 142 #define CONFIG_SYS_FLASH_BASE 0xec000000 143 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 144 145 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 146 147 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 148 #define CONFIG_SYS_MAX_FLASH_BANKS 1 149 150 #define CONFIG_SYS_FLASH_QUIET_TEST 151 #define CONFIG_FLASH_SHOW_PROGRESS 45 152 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 153 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 154 155 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 156 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 157 CSPR_PORT_SIZE_16 | \ 158 CSPR_MSEL_NOR | \ 159 CSPR_V) 160 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 161 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 162 163 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 164 FTIM0_NOR_TEADC(0x5) | \ 165 FTIM0_NOR_TEAHC(0x5)) 166 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 167 FTIM1_NOR_TRAD_NOR(0x1A) |\ 168 FTIM1_NOR_TSEQRAD_NOR(0x13)) 169 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 170 FTIM2_NOR_TCH(0x4) | \ 171 FTIM2_NOR_TWPH(0x0E) | \ 172 FTIM2_NOR_TWP(0x1c)) 173 #define CONFIG_SYS_NOR_FTIM3 0x0 174 175 /* CFI for NOR Flash */ 176 #define CONFIG_SYS_FLASH_EMPTY_INFO 177 178 /* NAND Flash on IFC */ 179 #define CONFIG_NAND_FSL_IFC 180 #define CONFIG_SYS_NAND_BASE 0xff800000 181 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 182 183 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 184 185 #define CONFIG_SYS_MAX_NAND_DEVICE 1 186 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 187 188 /* 8Bit NAND Flash - K9F1G08U0B */ 189 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 190 | CSPR_PORT_SIZE_8 \ 191 | CSPR_MSEL_NAND \ 192 | CSPR_V) 193 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 194 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 195 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 196 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 197 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 198 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 199 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 200 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 201 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 202 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 203 FTIM0_NAND_TWP(0x0c) | \ 204 FTIM0_NAND_TWCHT(0x08) | \ 205 FTIM0_NAND_TWH(0x06)) 206 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 207 FTIM1_NAND_TWBE(0x1d) | \ 208 FTIM1_NAND_TRR(0x08) | \ 209 FTIM1_NAND_TRP(0x0c)) 210 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 211 FTIM2_NAND_TREH(0x0a) | \ 212 FTIM2_NAND_TWHRE(0x18)) 213 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 214 215 #define CONFIG_SYS_NAND_DDR_LAW 11 216 217 /* Set up IFC registers for boot location NOR/NAND */ 218 #ifdef CONFIG_MTD_RAW_NAND 219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 222 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 223 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 224 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 225 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 226 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 227 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 228 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 229 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 230 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 231 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 232 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 233 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 234 #else 235 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 236 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 237 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 238 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 239 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 240 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 241 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 242 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 243 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 244 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 245 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 246 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 247 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 248 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 249 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 250 #endif 251 252 /* CPLD on IFC, selected by CS2 */ 253 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 254 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 255 | CONFIG_SYS_CPLD_BASE) 256 257 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 258 | CSPR_PORT_SIZE_8 \ 259 | CSPR_MSEL_GPCM \ 260 | CSPR_V) 261 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 262 #define CONFIG_SYS_CSOR2 0x0 263 /* CPLD Timing parameters for IFC CS2 */ 264 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 265 FTIM0_GPCM_TEADC(0x0e) | \ 266 FTIM0_GPCM_TEAHC(0x0e)) 267 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 268 FTIM1_GPCM_TRAD(0x1f)) 269 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 270 FTIM2_GPCM_TCH(0x8) | \ 271 FTIM2_GPCM_TWP(0x1f)) 272 #define CONFIG_SYS_CS2_FTIM3 0x0 273 274 #if defined(CONFIG_RAMBOOT_SPIFLASH) 275 #define CONFIG_SYS_RAMBOOT 276 #endif 277 278 #define CONFIG_SYS_INIT_RAM_LOCK 279 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 280 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 281 282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 283 - GENERATED_GBL_DATA_SIZE) 284 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 285 286 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 287 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 288 289 /* 290 * Config the L2 Cache as L2 SRAM 291 */ 292 #if defined(CONFIG_SPL_BUILD) 293 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 294 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 295 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 296 #define CONFIG_SYS_L2_SIZE (256 << 10) 297 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 298 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 299 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 300 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 301 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 302 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 303 #elif defined(CONFIG_MTD_RAW_NAND) 304 #ifdef CONFIG_TPL_BUILD 305 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 306 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 307 #define CONFIG_SYS_L2_SIZE (256 << 10) 308 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 309 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 310 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 311 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 312 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 313 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 314 #else 315 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 316 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 317 #define CONFIG_SYS_L2_SIZE (256 << 10) 318 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 319 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 320 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 321 #endif 322 #endif 323 #endif 324 325 /* Serial Port */ 326 #define CONFIG_SYS_NS16550_SERIAL 327 #define CONFIG_SYS_NS16550_REG_SIZE 1 328 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 329 330 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 331 #define CONFIG_NS16550_MIN_FUNCTIONS 332 #endif 333 334 #define CONFIG_SYS_BAUDRATE_TABLE \ 335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 336 337 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 338 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 339 340 #define CONFIG_SYS_I2C 341 #define CONFIG_SYS_I2C_FSL 342 #define CONFIG_SYS_FSL_I2C_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 344 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 345 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 346 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 347 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 348 349 /* I2C EEPROM */ 350 /* enable read and write access to EEPROM */ 351 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 353 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 354 355 /* eSPI - Enhanced SPI */ 356 357 #ifdef CONFIG_TSEC_ENET 358 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 359 #define CONFIG_TSEC1 1 360 #define CONFIG_TSEC1_NAME "eTSEC1" 361 #define CONFIG_TSEC2 1 362 #define CONFIG_TSEC2_NAME "eTSEC2" 363 364 /* Default mode is RGMII mode */ 365 #define TSEC1_PHY_ADDR 0 366 #define TSEC2_PHY_ADDR 2 367 368 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 369 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 370 371 #define CONFIG_ETHPRIME "eTSEC1" 372 #endif /* CONFIG_TSEC_ENET */ 373 374 /* 375 * Environment 376 */ 377 #if defined(CONFIG_SYS_RAMBOOT) 378 #elif defined(CONFIG_MTD_RAW_NAND) 379 #ifdef CONFIG_TPL_BUILD 380 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 381 #else 382 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 383 #endif 384 #endif 385 386 #define CONFIG_LOADS_ECHO 387 #define CONFIG_SYS_LOADS_BAUD_CHANGE 388 389 /* 390 * Miscellaneous configurable options 391 */ 392 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 393 394 /* 395 * For booting Linux, the board info and command line data 396 * have to be in the first 64 MB of memory, since this is 397 * the maximum mapped by the Linux kernel during initialization. 398 */ 399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 401 402 /* 403 * Environment Configuration 404 */ 405 406 #ifdef CONFIG_TSEC_ENET 407 #define CONFIG_HAS_ETH0 408 #define CONFIG_HAS_ETH1 409 #endif 410 411 #define CONFIG_ROOTPATH "/opt/nfsroot" 412 #define CONFIG_BOOTFILE "uImage" 413 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 414 415 /* default location for tftp and bootm */ 416 #define CONFIG_LOADADDR 1000000 417 418 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 419 420 #define CONFIG_EXTRA_ENV_SETTINGS \ 421 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 422 "netdev=eth0\0" \ 423 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 424 "loadaddr=1000000\0" \ 425 "consoledev=ttyS0\0" \ 426 "ramdiskaddr=2000000\0" \ 427 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 428 "fdtaddr=1e00000\0" \ 429 "fdtfile=name/of/device-tree.dtb\0" \ 430 "othbootargs=ramdisk_size=600000\0" \ 431 432 #define CONFIG_RAMBOOTCOMMAND \ 433 "setenv bootargs root=/dev/ram rw " \ 434 "console=$consoledev,$baudrate $othbootargs; " \ 435 "tftp $ramdiskaddr $ramdiskfile;" \ 436 "tftp $loadaddr $bootfile;" \ 437 "tftp $fdtaddr $fdtfile;" \ 438 "bootm $loadaddr $ramdiskaddr $fdtaddr" 439 440 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 441 442 #include <asm/fsl_secure_boot.h> 443 444 #endif /* __CONFIG_H */ 445