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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Freescale MCF5329 FireEngine board.
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 /*
10  * board/config.h - configuration options, board specific
11  */
12 
13 #ifndef _M5235EVB_H
14 #define _M5235EVB_H
15 
16 /*
17  * High Level Configuration Options
18  * (easy to change)
19  */
20 
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT		(0)
23 
24 #undef CONFIG_WATCHDOG
25 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
26 
27 /*
28  * BOOTP options
29  */
30 #define CONFIG_BOOTP_BOOTFILESIZE
31 
32 #define CONFIG_MCFFEC
33 #ifdef CONFIG_MCFFEC
34 #	define CONFIG_MII_INIT		1
35 #	define CONFIG_SYS_DISCOVER_PHY
36 #	define CONFIG_SYS_RX_ETH_BUFFER	8
37 #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
38 
39 #	define CONFIG_SYS_FEC0_PINMUX		0
40 #	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
41 #	define MCFFEC_TOUT_LOOP		50000
42 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
43 #	ifndef CONFIG_SYS_DISCOVER_PHY
44 #		define FECDUPLEX	FULL
45 #		define FECSPEED		_100BASET
46 #	else
47 #		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
48 #			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
49 #		endif
50 #	endif			/* CONFIG_SYS_DISCOVER_PHY */
51 #endif
52 
53 /* Timer */
54 #define CONFIG_MCFTMR
55 #undef CONFIG_MCFPIT
56 
57 /* I2C */
58 #define CONFIG_SYS_I2C
59 #define CONFIG_SYS_i2C_FSL
60 #define CONFIG_SYS_FSL_I2C_SPEED	80000
61 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
62 #define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
63 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
64 #define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
65 #define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
66 #define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
67 
68 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
69 #define CONFIG_BOOTFILE		"u-boot.bin"
70 #ifdef CONFIG_MCFFEC
71 #	define CONFIG_IPADDR	192.162.1.2
72 #	define CONFIG_NETMASK	255.255.255.0
73 #	define CONFIG_SERVERIP	192.162.1.1
74 #	define CONFIG_GATEWAYIP	192.162.1.1
75 #endif				/* FEC_ENET */
76 
77 #define CONFIG_HOSTNAME		"M5235EVB"
78 #define CONFIG_EXTRA_ENV_SETTINGS		\
79 	"netdev=eth0\0"				\
80 	"loadaddr=10000\0"			\
81 	"u-boot=u-boot.bin\0"			\
82 	"load=tftp ${loadaddr) ${u-boot}\0"	\
83 	"upd=run load; run prog\0"		\
84 	"prog=prot off ffe00000 ffe3ffff;"	\
85 	"era ffe00000 ffe3ffff;"		\
86 	"cp.b ${loadaddr} ffe00000 ${filesize};"\
87 	"save\0"				\
88 	""
89 
90 #define CONFIG_PRAM		512	/* 512 KB */
91 
92 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
93 
94 #define CONFIG_SYS_CLK			75000000
95 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
96 
97 #define CONFIG_SYS_MBAR		0x40000000
98 
99 /*
100  * Low Level Configuration Settings
101  * (address mappings, register initial values, etc.)
102  * You should know what you are doing if you make changes here.
103  */
104 /*-----------------------------------------------------------------------
105  * Definitions for initial stack pointer and data area (in DPRAM)
106  */
107 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
108 #define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
109 #define CONFIG_SYS_INIT_RAM_CTRL	0x21
110 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
111 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
112 
113 /*-----------------------------------------------------------------------
114  * Start addresses for the final memory configuration
115  * (Set up by the startup code)
116  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
117  */
118 #define CONFIG_SYS_SDRAM_BASE		0x00000000
119 #define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
120 
121 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
122 #define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
123 
124 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
125 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
126 
127 #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
128 #define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
129 
130 /*
131  * For booting Linux, the board info and command line data
132  * have to be in the first 8 MB of memory, since this is
133  * the maximum mapped by the Linux kernel during initialization ??
134  */
135 /* Initial Memory map for Linux */
136 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
137 #define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
138 
139 /*-----------------------------------------------------------------------
140  * FLASH organization
141  */
142 #ifdef CONFIG_SYS_FLASH_CFI
143 #	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
144 #ifdef NORFLASH_PS32BIT
145 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
146 #else
147 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
148 #endif
149 #	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
150 #	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
151 #endif
152 
153 #define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
154 
155 /* Configuration for environment
156  * Environment is embedded in u-boot in the second sector of the flash
157  */
158 
159 #define LDS_BOARD_TEXT \
160 	. = DEFINED(env_offset) ? env_offset : .; \
161 	env/embedded.o(.text);
162 
163 /*-----------------------------------------------------------------------
164  * Cache Configuration
165  */
166 #define CONFIG_SYS_CACHELINE_SIZE	16
167 
168 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
169 					 CONFIG_SYS_INIT_RAM_SIZE - 8)
170 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
171 					 CONFIG_SYS_INIT_RAM_SIZE - 4)
172 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
173 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
174 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
175 					 CF_ACR_EN | CF_ACR_SM_ALL)
176 #define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
177 					 CF_CACR_CEIB | CF_CACR_DCM | \
178 					 CF_CACR_EUSP)
179 
180 /*-----------------------------------------------------------------------
181  * Chipselect bank definitions
182  */
183 /*
184  * CS0 - NOR Flash 1, 2, 4, or 8MB
185  * CS1 - Available
186  * CS2 - Available
187  * CS3 - Available
188  * CS4 - Available
189  * CS5 - Available
190  * CS6 - Available
191  * CS7 - Available
192  */
193 #ifdef NORFLASH_PS32BIT
194 #	define CONFIG_SYS_CS0_BASE	0xFFC00000
195 #	define CONFIG_SYS_CS0_MASK	0x003f0001
196 #	define CONFIG_SYS_CS0_CTRL	0x00001D00
197 #else
198 #	define CONFIG_SYS_CS0_BASE	0xFFE00000
199 #	define CONFIG_SYS_CS0_MASK	0x001f0001
200 #	define CONFIG_SYS_CS0_CTRL	0x00001D80
201 #endif
202 
203 #endif				/* _M5329EVB_H */
204