1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 4 */ 5 /* 6 * mpc8313epb board configuration file 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 16 17 #define CONFIG_SPL_INIT_MINIMAL 18 #define CONFIG_SPL_FLUSH_IMAGE 19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 21 22 #ifdef CONFIG_SPL_BUILD 23 #define CONFIG_NS16550_MIN_FUNCTIONS 24 #endif 25 26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 27 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 28 #define CONFIG_SPL_PAD_TO 0x4000 29 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 36 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 39 #endif 40 41 #ifndef CONFIG_SYS_MONITOR_BASE 42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 43 #endif 44 45 #define CONFIG_PCI_INDIRECT_BRIDGE 46 #define CONFIG_FSL_ELBC 1 47 48 /* 49 * On-board devices 50 * 51 * TSEC1 is VSC switch 52 * TSEC2 is SoC TSEC 53 */ 54 #define CONFIG_VSC7385_ENET 55 #define CONFIG_TSEC2 56 57 #if !defined(CONFIG_SPL_BUILD) 58 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 59 #endif 60 61 #define CONFIG_SYS_MEMTEST_START 0x00001000 62 #define CONFIG_SYS_MEMTEST_END 0x07f00000 63 64 /* Early revs of this board will lock up hard when attempting 65 * to access the PMC registers, unless a JTAG debugger is 66 * connected, or some resistor modifications are made. 67 */ 68 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 69 70 /* 71 * Device configurations 72 */ 73 74 /* Vitesse 7385 */ 75 76 #ifdef CONFIG_VSC7385_ENET 77 78 #define CONFIG_TSEC1 79 80 /* The flash address and size of the VSC7385 firmware image */ 81 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 82 #define CONFIG_VSC7385_IMAGE_SIZE 8192 83 84 #endif 85 86 /* 87 * DDR Setup 88 */ 89 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 90 91 /* 92 * Manually set up DDR parameters, as this board does not 93 * seem to have the SPD connected to I2C. 94 */ 95 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 96 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 97 | CSCONFIG_ODT_RD_NEVER \ 98 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 99 | CSCONFIG_ROW_BIT_13 \ 100 | CSCONFIG_COL_BIT_10) 101 /* 0x80010102 */ 102 103 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 104 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 105 | (0 << TIMING_CFG0_WRT_SHIFT) \ 106 | (0 << TIMING_CFG0_RRT_SHIFT) \ 107 | (0 << TIMING_CFG0_WWT_SHIFT) \ 108 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 109 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 110 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 111 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 112 /* 0x00220802 */ 113 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 114 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 115 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 116 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 117 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 118 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 119 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 120 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 121 /* 0x3835a322 */ 122 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 123 | (5 << TIMING_CFG2_CPO_SHIFT) \ 124 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 125 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 126 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 127 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 128 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 129 /* 0x129048c6 */ /* P9-45,may need tuning */ 130 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 131 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 132 /* 0x05100500 */ 133 #if defined(CONFIG_DDR_2T_TIMING) 134 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 135 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 136 | SDRAM_CFG_DBW_32 \ 137 | SDRAM_CFG_2T_EN) 138 /* 0x43088000 */ 139 #else 140 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 141 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 142 | SDRAM_CFG_DBW_32) 143 /* 0x43080000 */ 144 #endif 145 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 146 /* set burst length to 8 for 32-bit data path */ 147 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 148 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 149 /* 0x44480632 */ 150 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 151 152 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 153 /*0x02000000*/ 154 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 155 | DDRCDR_PZ_NOMZ \ 156 | DDRCDR_NZ_NOMZ \ 157 | DDRCDR_M_ODR) 158 159 /* 160 * FLASH on the Local Bus 161 */ 162 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 163 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 164 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 165 166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 167 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 168 169 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 170 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 171 172 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 173 !defined(CONFIG_SPL_BUILD) 174 #define CONFIG_SYS_RAMBOOT 175 #endif 176 177 #define CONFIG_SYS_INIT_RAM_LOCK 1 178 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 180 181 #define CONFIG_SYS_GBL_DATA_OFFSET \ 182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 185 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 186 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 187 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 188 189 /* drivers/mtd/nand/raw/nand.c */ 190 #if defined(CONFIG_SPL_BUILD) 191 #define CONFIG_SYS_NAND_BASE 0xFFF00000 192 #else 193 #define CONFIG_SYS_NAND_BASE 0xE2800000 194 #endif 195 196 #define CONFIG_MTD_PARTITION 197 198 #define CONFIG_SYS_MAX_NAND_DEVICE 1 199 #define CONFIG_NAND_FSL_ELBC 1 200 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 201 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 202 203 /* Still needed for spl_minimal.c */ 204 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM 205 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM 206 207 /* local bus write LED / read status buffer (BCSR) mapping */ 208 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 209 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 210 /* map at 0xFA000000 on LCS3 */ 211 212 /* Vitesse 7385 */ 213 214 #ifdef CONFIG_VSC7385_ENET 215 216 /* VSC7385 Base address on LCS2 */ 217 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 218 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 219 220 221 #endif 222 223 #define CONFIG_MPC83XX_GPIO 1 224 225 /* 226 * Serial Port 227 */ 228 #define CONFIG_SYS_NS16550_SERIAL 229 #define CONFIG_SYS_NS16550_REG_SIZE 1 230 231 #define CONFIG_SYS_BAUDRATE_TABLE \ 232 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 233 234 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 235 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 236 237 /* I2C */ 238 #define CONFIG_SYS_I2C 239 #define CONFIG_SYS_I2C_FSL 240 #define CONFIG_SYS_FSL_I2C_SPEED 400000 241 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 243 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 244 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 245 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 246 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 247 248 /* 249 * General PCI 250 * Addresses are mapped 1-1. 251 */ 252 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 253 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 254 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 255 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 256 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 257 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 258 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 259 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 260 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 261 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 263 264 /* 265 * TSEC 266 */ 267 268 #define CONFIG_GMII /* MII PHY management */ 269 270 #ifdef CONFIG_TSEC1 271 #define CONFIG_HAS_ETH0 272 #define CONFIG_TSEC1_NAME "TSEC0" 273 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 274 #define TSEC1_PHY_ADDR 0x1c 275 #define TSEC1_FLAGS TSEC_GIGABIT 276 #define TSEC1_PHYIDX 0 277 #endif 278 279 #ifdef CONFIG_TSEC2 280 #define CONFIG_HAS_ETH1 281 #define CONFIG_TSEC2_NAME "TSEC1" 282 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 283 #define TSEC2_PHY_ADDR 4 284 #define TSEC2_FLAGS TSEC_GIGABIT 285 #define TSEC2_PHYIDX 0 286 #endif 287 288 /* Options are: TSEC[0-1] */ 289 #define CONFIG_ETHPRIME "TSEC1" 290 291 /* 292 * Configure on-board RTC 293 */ 294 #define CONFIG_RTC_DS1337 295 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 296 297 /* 298 * Environment 299 */ 300 #define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4) 301 302 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 303 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 304 305 /* 306 * BOOTP options 307 */ 308 #define CONFIG_BOOTP_BOOTFILESIZE 309 310 /* 311 * Command line configuration. 312 */ 313 314 /* 315 * Miscellaneous configurable options 316 */ 317 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 318 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 319 320 /* Boot Argument Buffer Size */ 321 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 322 323 /* 324 * For booting Linux, the board info and command line data 325 * have to be in the first 256 MB of memory, since this is 326 * the maximum mapped by the Linux kernel during initialization. 327 */ 328 /* Initial Memory map for Linux*/ 329 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 330 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 331 332 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 333 334 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 335 336 /* System IO Config */ 337 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 338 /* Enable Internal USB Phy and GPIO on LCD Connector */ 339 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 340 341 /* 342 * Environment Configuration 343 */ 344 #define CONFIG_ENV_OVERWRITE 345 346 #define CONFIG_NETDEV "eth1" 347 348 #define CONFIG_HOSTNAME "mpc8313erdb" 349 #define CONFIG_ROOTPATH "/nfs/root/path" 350 #define CONFIG_BOOTFILE "uImage" 351 /* U-Boot image on TFTP server */ 352 #define CONFIG_UBOOTPATH "u-boot.bin" 353 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 354 355 /* default location for tftp and bootm */ 356 #define CONFIG_LOADADDR 800000 357 358 #define CONFIG_EXTRA_ENV_SETTINGS \ 359 "netdev=" CONFIG_NETDEV "\0" \ 360 "ethprime=TSEC1\0" \ 361 "uboot=" CONFIG_UBOOTPATH "\0" \ 362 "tftpflash=tftpboot $loadaddr $uboot; " \ 363 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 364 " +$filesize; " \ 365 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 366 " +$filesize; " \ 367 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 368 " $filesize; " \ 369 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 370 " +$filesize; " \ 371 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 372 " $filesize\0" \ 373 "fdtaddr=780000\0" \ 374 "fdtfile=" CONFIG_FDTFILE "\0" \ 375 "console=ttyS0\0" \ 376 "setbootargs=setenv bootargs " \ 377 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 378 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 379 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 380 "$netdev:off " \ 381 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 382 383 #define CONFIG_NFSBOOTCOMMAND \ 384 "setenv rootdev /dev/nfs;" \ 385 "run setbootargs;" \ 386 "run setipargs;" \ 387 "tftp $loadaddr $bootfile;" \ 388 "tftp $fdtaddr $fdtfile;" \ 389 "bootm $loadaddr - $fdtaddr" 390 391 #define CONFIG_RAMBOOTCOMMAND \ 392 "setenv rootdev /dev/ram;" \ 393 "run setbootargs;" \ 394 "tftp $ramdiskaddr $ramdiskfile;" \ 395 "tftp $loadaddr $bootfile;" \ 396 "tftp $fdtaddr $fdtfile;" \ 397 "bootm $loadaddr $ramdiskaddr $fdtaddr" 398 399 #endif /* __CONFIG_H */ 400