1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P2041 RDB board configuration file 8 * Also supports P2040 RDB 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 31 #ifndef CONFIG_RESET_VECTOR_ADDRESS 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 37 #define CONFIG_PCIE1 /* PCIE controller 1 */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 */ 39 #define CONFIG_PCIE3 /* PCIE controller 3 */ 40 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 41 42 #define CONFIG_SYS_SRIO 43 #define CONFIG_SRIO1 /* SRIO port 1 */ 44 #define CONFIG_SRIO2 /* SRIO port 2 */ 45 #define CONFIG_SRIO_PCIE_BOOT_MASTER 46 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 47 48 #define CONFIG_ENV_OVERWRITE 49 50 #if defined(CONFIG_SPIFLASH) 51 #elif defined(CONFIG_SDCARD) 52 #define CONFIG_FSL_FIXED_MMC_LOCATION 53 #define CONFIG_SYS_MMC_ENV_DEV 0 54 #endif 55 56 #ifndef __ASSEMBLY__ 57 unsigned long get_board_sys_clk(unsigned long dummy); 58 #endif 59 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_SYS_CACHE_STASHING 65 #define CONFIG_BACKSIDE_L2_CACHE 66 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 67 #define CONFIG_BTB /* toggle branch predition */ 68 69 #define CONFIG_ENABLE_36BIT_PHYS 70 71 #ifdef CONFIG_PHYS_64BIT 72 #define CONFIG_ADDR_MAP 73 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 74 #endif 75 76 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * Config the L3 Cache as L3 SRAM 82 */ 83 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 84 #ifdef CONFIG_PHYS_64BIT 85 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 86 CONFIG_RAMBOOT_TEXT_BASE) 87 #else 88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 89 #endif 90 #define CONFIG_SYS_L3_SIZE (1024 << 10) 91 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 92 93 #ifdef CONFIG_PHYS_64BIT 94 #define CONFIG_SYS_DCSRBAR 0xf0000000 95 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 96 #endif 97 98 /* EEPROM */ 99 #define CONFIG_ID_EEPROM 100 #define CONFIG_SYS_I2C_EEPROM_NXID 101 #define CONFIG_SYS_EEPROM_BUS_NUM 0 102 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_VERY_BIG_RAM 109 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 111 112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 113 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 114 115 #define CONFIG_DDR_SPD 116 117 #define CONFIG_SYS_SPD_BUS_NUM 0 118 #define SPD_EEPROM_ADDRESS 0x52 119 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 120 121 /* 122 * Local Bus Definitions 123 */ 124 125 /* Set the local bus clock 1/8 of platform clock */ 126 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 127 128 /* 129 * This board doesn't have a promjet connector. 130 * However, it uses commone corenet board LAW and TLB. 131 * It is necessary to use the same start address with proper offset. 132 */ 133 #define CONFIG_SYS_FLASH_BASE 0xe0000000 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 136 #else 137 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 138 #endif 139 140 #define CONFIG_SYS_FLASH_BR_PRELIM \ 141 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 142 BR_PS_16 | BR_V) 143 #define CONFIG_SYS_FLASH_OR_PRELIM \ 144 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 145 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 146 147 #define CONFIG_FSL_CPLD 148 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 149 #ifdef CONFIG_PHYS_64BIT 150 #define CPLD_BASE_PHYS 0xfffdf0000ull 151 #else 152 #define CPLD_BASE_PHYS CPLD_BASE 153 #endif 154 155 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 156 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 157 158 #define PIXIS_LBMAP_SWITCH 7 159 #define PIXIS_LBMAP_MASK 0xf0 160 #define PIXIS_LBMAP_SHIFT 4 161 #define PIXIS_LBMAP_ALTBANK 0x40 162 163 #define CONFIG_SYS_FLASH_QUIET_TEST 164 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 165 166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 167 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 170 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 172 173 #if defined(CONFIG_RAMBOOT_PBL) 174 #define CONFIG_SYS_RAMBOOT 175 #endif 176 177 #define CONFIG_NAND_FSL_ELBC 178 /* Nand Flash */ 179 #ifdef CONFIG_NAND_FSL_ELBC 180 #define CONFIG_SYS_NAND_BASE 0xffa00000 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 183 #else 184 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 185 #endif 186 187 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 188 #define CONFIG_SYS_MAX_NAND_DEVICE 1 189 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 190 191 /* NAND flash config */ 192 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 193 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 194 | BR_PS_8 /* Port Size = 8 bit */ \ 195 | BR_MS_FCM /* MSEL = FCM */ \ 196 | BR_V) /* valid */ 197 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 198 | OR_FCM_PGS /* Large Page*/ \ 199 | OR_FCM_CSCT \ 200 | OR_FCM_CST \ 201 | OR_FCM_CHT \ 202 | OR_FCM_SCY_1 \ 203 | OR_FCM_TRLX \ 204 | OR_FCM_EHTR) 205 206 #ifdef CONFIG_MTD_RAW_NAND 207 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 208 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 209 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 210 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 211 #else 212 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 213 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 214 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 215 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 216 #endif 217 #else 218 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 219 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 220 #endif /* CONFIG_NAND_FSL_ELBC */ 221 222 #define CONFIG_SYS_FLASH_EMPTY_INFO 223 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 225 226 #define CONFIG_HWCONFIG 227 228 /* define to use L1 as initial stack */ 229 #define CONFIG_L1_INIT_RAM 230 #define CONFIG_SYS_INIT_RAM_LOCK 231 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 235 /* The assembler doesn't like typecast */ 236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 237 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 238 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 239 #else 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 243 #endif 244 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 245 246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 247 GENERATED_GBL_DATA_SIZE) 248 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 249 250 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 251 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 252 253 /* Serial Port - controlled on board with jumper J8 254 * open - index 2 255 * shorted - index 1 256 */ 257 #define CONFIG_SYS_NS16550_SERIAL 258 #define CONFIG_SYS_NS16550_REG_SIZE 1 259 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 260 261 #define CONFIG_SYS_BAUDRATE_TABLE \ 262 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 263 264 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 265 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 266 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 267 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 268 269 /* I2C */ 270 #define CONFIG_SYS_I2C 271 #define CONFIG_SYS_I2C_FSL 272 #define CONFIG_SYS_FSL_I2C_SPEED 400000 273 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 274 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 275 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 276 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 277 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 278 279 /* 280 * RapidIO 281 */ 282 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 285 #else 286 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 287 #endif 288 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 289 290 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 293 #else 294 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 295 #endif 296 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 297 298 /* 299 * for slave u-boot IMAGE instored in master memory space, 300 * PHYS must be aligned based on the SIZE 301 */ 302 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 303 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 304 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 305 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 306 /* 307 * for slave UCODE and ENV instored in master memory space, 308 * PHYS must be aligned based on the SIZE 309 */ 310 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 311 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 312 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 313 314 /* slave core release by master*/ 315 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 316 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 317 318 /* 319 * SRIO_PCIE_BOOT - SLAVE 320 */ 321 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 322 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 323 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 324 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 325 #endif 326 327 /* 328 * eSPI - Enhanced SPI 329 */ 330 331 /* 332 * General PCI 333 * Memory space is mapped 1-1, but I/O space must start from 0. 334 */ 335 336 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 337 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 338 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 339 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 340 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 341 342 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 343 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 344 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 345 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 346 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 347 348 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 349 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 350 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 351 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 352 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 353 354 /* Qman/Bman */ 355 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 356 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 359 #else 360 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 361 #endif 362 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 363 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 364 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 365 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 366 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 367 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 368 CONFIG_SYS_BMAN_CENA_SIZE) 369 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 370 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 371 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 372 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 375 #else 376 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 377 #endif 378 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 379 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 380 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 381 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 382 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 383 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 384 CONFIG_SYS_QMAN_CENA_SIZE) 385 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 386 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 387 388 #define CONFIG_SYS_DPAA_FMAN 389 #define CONFIG_SYS_DPAA_PME 390 /* Default address of microcode for the Linux Fman driver */ 391 #if defined(CONFIG_SPIFLASH) 392 /* 393 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 394 * env, so we got 0x110000. 395 */ 396 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 397 #elif defined(CONFIG_SDCARD) 398 /* 399 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 400 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 401 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 402 */ 403 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 404 #elif defined(CONFIG_MTD_RAW_NAND) 405 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 406 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 407 /* 408 * Slave has no ucode locally, it can fetch this from remote. When implementing 409 * in two corenet boards, slave's ucode could be stored in master's memory 410 * space, the address can be mapped from slave TLB->slave LAW-> 411 * slave SRIO or PCIE outbound window->master inbound window-> 412 * master LAW->the ucode address in master's memory space. 413 */ 414 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 415 #else 416 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 417 #endif 418 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 419 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 420 421 #ifdef CONFIG_SYS_DPAA_FMAN 422 #define CONFIG_PHYLIB_10G 423 #define CONFIG_PHY_VITESSE 424 #define CONFIG_PHY_TERANETICS 425 #endif 426 427 #ifdef CONFIG_PCI 428 #if !defined(CONFIG_DM_PCI) 429 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 430 #define CONFIG_PCI_INDIRECT_BRIDGE 431 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 432 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 433 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 434 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 435 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 436 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 437 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 438 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 439 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 440 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 442 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 443 #endif 444 445 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 446 #endif /* CONFIG_PCI */ 447 448 /* SATA */ 449 #define CONFIG_FSL_SATA_V2 450 451 #ifdef CONFIG_FSL_SATA_V2 452 #define CONFIG_SYS_SATA_MAX_DEVICE 2 453 #define CONFIG_SATA1 454 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 455 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 456 #define CONFIG_SATA2 457 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 458 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 459 460 #define CONFIG_LBA48 461 #endif 462 463 #ifdef CONFIG_FMAN_ENET 464 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 465 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 466 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 467 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 468 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 469 470 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 471 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 472 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 473 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 474 475 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 476 477 #define CONFIG_SYS_TBIPA_VALUE 8 478 #define CONFIG_ETHPRIME "FM1@DTSEC1" 479 #endif 480 481 /* 482 * Environment 483 */ 484 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 485 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 486 487 /* 488 * Command line configuration. 489 */ 490 491 /* 492 * USB 493 */ 494 #define CONFIG_HAS_FSL_DR_USB 495 #define CONFIG_HAS_FSL_MPH_USB 496 497 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 498 #define CONFIG_USB_EHCI_FSL 499 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 500 #endif 501 502 #ifdef CONFIG_MMC 503 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 504 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 505 #endif 506 507 /* 508 * Miscellaneous configurable options 509 */ 510 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 511 512 /* 513 * For booting Linux, the board info and command line data 514 * have to be in the first 64 MB of memory, since this is 515 * the maximum mapped by the Linux kernel during initialization. 516 */ 517 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 518 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 519 520 #ifdef CONFIG_CMD_KGDB 521 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 522 #endif 523 524 /* 525 * Environment Configuration 526 */ 527 #define CONFIG_ROOTPATH "/opt/nfsroot" 528 #define CONFIG_BOOTFILE "uImage" 529 #define CONFIG_UBOOTPATH u-boot.bin 530 531 /* default location for tftp and bootm */ 532 #define CONFIG_LOADADDR 1000000 533 534 #define __USB_PHY_TYPE utmi 535 536 #define CONFIG_EXTRA_ENV_SETTINGS \ 537 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 538 "bank_intlv=cs0_cs1\0" \ 539 "netdev=eth0\0" \ 540 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 541 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 542 "tftpflash=tftpboot $loadaddr $uboot && " \ 543 "protect off $ubootaddr +$filesize && " \ 544 "erase $ubootaddr +$filesize && " \ 545 "cp.b $loadaddr $ubootaddr $filesize && " \ 546 "protect on $ubootaddr +$filesize && " \ 547 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 548 "consoledev=ttyS0\0" \ 549 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 550 "usb_dr_mode=host\0" \ 551 "ramdiskaddr=2000000\0" \ 552 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 553 "fdtaddr=1e00000\0" \ 554 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 555 "bdev=sda3\0" 556 557 #define CONFIG_HDBOOT \ 558 "setenv bootargs root=/dev/$bdev rw " \ 559 "console=$consoledev,$baudrate $othbootargs;" \ 560 "tftp $loadaddr $bootfile;" \ 561 "tftp $fdtaddr $fdtfile;" \ 562 "bootm $loadaddr - $fdtaddr" 563 564 #define CONFIG_NFSBOOTCOMMAND \ 565 "setenv bootargs root=/dev/nfs rw " \ 566 "nfsroot=$serverip:$rootpath " \ 567 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 568 "console=$consoledev,$baudrate $othbootargs;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr - $fdtaddr" 572 573 #define CONFIG_RAMBOOTCOMMAND \ 574 "setenv bootargs root=/dev/ram rw " \ 575 "console=$consoledev,$baudrate $othbootargs;" \ 576 "tftp $ramdiskaddr $ramdiskfile;" \ 577 "tftp $loadaddr $bootfile;" \ 578 "tftp $fdtaddr $fdtfile;" \ 579 "bootm $loadaddr $ramdiskaddr $fdtaddr" 580 581 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 582 583 #include <asm/fsl_secure_boot.h> 584 585 #endif /* __CONFIG_H */ 586