1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080/T2081 QDS board configuration file 8 */ 9 10 #ifndef __T208xQDS_H 11 #define __T208xQDS_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #if defined(CONFIG_ARCH_T2080) 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 #define CONFIG_SRIO2 /* SRIO port 2 */ 19 #elif defined(CONFIG_ARCH_T2081) 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_ENABLE_36BIT_PHYS 25 26 #ifdef CONFIG_PHYS_64BIT 27 #define CONFIG_ADDR_MAP 1 28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 #define CONFIG_ENV_OVERWRITE 34 35 #ifdef CONFIG_RAMBOOT_PBL 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 37 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #endif 48 49 #ifdef CONFIG_MTD_RAW_NAND 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #if defined(CONFIG_ARCH_T2080) 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 56 #elif defined(CONFIG_ARCH_T2081) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 58 #endif 59 #endif 60 61 #ifdef CONFIG_SPIFLASH 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 63 #define CONFIG_SPL_SPI_FLASH_MINIMAL 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #if defined(CONFIG_ARCH_T2080) 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 73 #elif defined(CONFIG_ARCH_T2081) 74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 75 #endif 76 #endif 77 78 #ifdef CONFIG_SDCARD 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 80 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 82 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 83 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #if defined(CONFIG_ARCH_T2080) 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 89 #elif defined(CONFIG_ARCH_T2081) 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 91 #endif 92 #endif 93 94 #endif /* CONFIG_RAMBOOT_PBL */ 95 96 #define CONFIG_SRIO_PCIE_BOOT_MASTER 97 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 98 /* Set 1M boot space */ 99 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 100 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 101 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 102 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 103 #endif 104 105 #ifndef CONFIG_RESET_VECTOR_ADDRESS 106 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 107 #endif 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BTB /* toggle branch predition */ 114 #define CONFIG_DDR_ECC 115 #ifdef CONFIG_DDR_ECC 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 117 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 118 #endif 119 120 #if defined(CONFIG_SPIFLASH) 121 #elif defined(CONFIG_SDCARD) 122 #define CONFIG_SYS_MMC_ENV_DEV 0 123 #endif 124 125 #ifndef __ASSEMBLY__ 126 unsigned long get_board_sys_clk(void); 127 unsigned long get_board_ddr_clk(void); 128 #endif 129 130 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 131 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 132 133 /* 134 * Config the L3 Cache as L3 SRAM 135 */ 136 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 137 #define CONFIG_SYS_L3_SIZE (512 << 10) 138 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 139 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 140 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 141 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 142 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 143 144 #define CONFIG_SYS_DCSRBAR 0xf0000000 145 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 146 147 /* EEPROM */ 148 #define CONFIG_ID_EEPROM 149 #define CONFIG_SYS_I2C_EEPROM_NXID 150 #define CONFIG_SYS_EEPROM_BUS_NUM 0 151 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 153 154 /* 155 * DDR Setup 156 */ 157 #define CONFIG_VERY_BIG_RAM 158 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 160 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 161 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 162 #define CONFIG_DDR_SPD 163 #define CONFIG_SYS_SPD_BUS_NUM 0 164 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 165 #define SPD_EEPROM_ADDRESS1 0x51 166 #define SPD_EEPROM_ADDRESS2 0x52 167 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 168 #define CTRL_INTLV_PREFERED cacheline 169 170 /* 171 * IFC Definitions 172 */ 173 #define CONFIG_SYS_FLASH_BASE 0xe0000000 174 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 175 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 176 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 177 + 0x8000000) | \ 178 CSPR_PORT_SIZE_16 | \ 179 CSPR_MSEL_NOR | \ 180 CSPR_V) 181 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 182 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 183 CSPR_PORT_SIZE_16 | \ 184 CSPR_MSEL_NOR | \ 185 CSPR_V) 186 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 187 /* NOR Flash Timing Params */ 188 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 189 190 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 191 FTIM0_NOR_TEADC(0x5) | \ 192 FTIM0_NOR_TEAHC(0x5)) 193 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 194 FTIM1_NOR_TRAD_NOR(0x1A) |\ 195 FTIM1_NOR_TSEQRAD_NOR(0x13)) 196 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 197 FTIM2_NOR_TCH(0x4) | \ 198 FTIM2_NOR_TWPH(0x0E) | \ 199 FTIM2_NOR_TWP(0x1c)) 200 #define CONFIG_SYS_NOR_FTIM3 0x0 201 202 #define CONFIG_SYS_FLASH_QUIET_TEST 203 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 209 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 212 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 213 214 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 215 #define QIXIS_BASE 0xffdf0000 216 #define QIXIS_LBMAP_SWITCH 6 217 #define QIXIS_LBMAP_MASK 0x0f 218 #define QIXIS_LBMAP_SHIFT 0 219 #define QIXIS_LBMAP_DFLTBANK 0x00 220 #define QIXIS_LBMAP_ALTBANK 0x04 221 #define QIXIS_LBMAP_NAND 0x09 222 #define QIXIS_LBMAP_SD 0x00 223 #define QIXIS_RCW_SRC_NAND 0x104 224 #define QIXIS_RCW_SRC_SD 0x040 225 #define QIXIS_RST_CTL_RESET 0x83 226 #define QIXIS_RST_FORCE_MEM 0x1 227 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 228 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 229 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 230 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 231 232 #define CONFIG_SYS_CSPR3_EXT (0xf) 233 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_GPCM \ 236 | CSPR_V) 237 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 238 #define CONFIG_SYS_CSOR3 0x0 239 /* QIXIS Timing parameters for IFC CS3 */ 240 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 241 FTIM0_GPCM_TEADC(0x0e) | \ 242 FTIM0_GPCM_TEAHC(0x0e)) 243 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 244 FTIM1_GPCM_TRAD(0x3f)) 245 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 246 FTIM2_GPCM_TCH(0x8) | \ 247 FTIM2_GPCM_TWP(0x1f)) 248 #define CONFIG_SYS_CS3_FTIM3 0x0 249 250 /* NAND Flash on IFC */ 251 #define CONFIG_NAND_FSL_IFC 252 #define CONFIG_SYS_NAND_BASE 0xff800000 253 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 254 255 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 256 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 257 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 258 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 259 | CSPR_V) 260 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 261 262 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 263 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 264 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 265 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 266 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 267 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 268 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 269 270 #define CONFIG_SYS_NAND_ONFI_DETECTION 271 272 /* ONFI NAND Flash mode0 Timing Params */ 273 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 274 FTIM0_NAND_TWP(0x18) | \ 275 FTIM0_NAND_TWCHT(0x07) | \ 276 FTIM0_NAND_TWH(0x0a)) 277 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 278 FTIM1_NAND_TWBE(0x39) | \ 279 FTIM1_NAND_TRR(0x0e) | \ 280 FTIM1_NAND_TRP(0x18)) 281 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 282 FTIM2_NAND_TREH(0x0a) | \ 283 FTIM2_NAND_TWHRE(0x1e)) 284 #define CONFIG_SYS_NAND_FTIM3 0x0 285 286 #define CONFIG_SYS_NAND_DDR_LAW 11 287 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 288 #define CONFIG_SYS_MAX_NAND_DEVICE 1 289 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 290 291 #if defined(CONFIG_MTD_RAW_NAND) 292 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 293 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 294 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 295 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 296 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 297 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 298 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 299 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 300 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 301 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 302 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 303 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 304 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 305 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 306 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 307 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 308 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 309 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 310 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #else 317 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 318 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 319 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 320 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 321 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 322 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 323 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 324 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 325 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 334 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 335 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 336 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 337 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 338 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 339 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 340 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 341 #endif 342 343 #if defined(CONFIG_RAMBOOT_PBL) 344 #define CONFIG_SYS_RAMBOOT 345 #endif 346 347 #ifdef CONFIG_SPL_BUILD 348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 349 #else 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 351 #endif 352 353 #define CONFIG_HWCONFIG 354 355 /* define to use L1 as initial stack */ 356 #define CONFIG_L1_INIT_RAM 357 #define CONFIG_SYS_INIT_RAM_LOCK 358 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 361 /* The assembler doesn't like typecast */ 362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 363 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 364 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 365 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 366 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 367 GENERATED_GBL_DATA_SIZE) 368 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 369 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 370 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 371 372 /* 373 * Serial Port 374 */ 375 #define CONFIG_SYS_NS16550_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 378 #define CONFIG_SYS_BAUDRATE_TABLE \ 379 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 380 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 381 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 382 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 383 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 384 385 /* 386 * I2C 387 */ 388 #define CONFIG_SYS_I2C 389 #define CONFIG_SYS_I2C_FSL 390 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 391 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 392 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 393 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 394 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 395 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 396 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 397 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 398 #define CONFIG_SYS_FSL_I2C_SPEED 100000 399 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 400 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 401 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 402 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 403 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 404 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 405 #define I2C_MUX_CH_DEFAULT 0x8 406 407 #define I2C_MUX_CH_VOL_MONITOR 0xa 408 409 /* Voltage monitor on channel 2*/ 410 #define I2C_VOL_MONITOR_ADDR 0x40 411 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 412 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 413 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 414 415 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 416 #ifndef CONFIG_SPL_BUILD 417 #define CONFIG_VID 418 #endif 419 #define CONFIG_VOL_MONITOR_IR36021_SET 420 #define CONFIG_VOL_MONITOR_IR36021_READ 421 /* The lowest and highest voltage allowed for T208xQDS */ 422 #define VDD_MV_MIN 819 423 #define VDD_MV_MAX 1212 424 425 /* 426 * RapidIO 427 */ 428 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 429 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 430 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 431 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 432 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 433 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 434 /* 435 * for slave u-boot IMAGE instored in master memory space, 436 * PHYS must be aligned based on the SIZE 437 */ 438 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 439 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 440 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 441 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 442 /* 443 * for slave UCODE and ENV instored in master memory space, 444 * PHYS must be aligned based on the SIZE 445 */ 446 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 447 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 448 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 449 450 /* slave core release by master*/ 451 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 452 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 453 454 /* 455 * SRIO_PCIE_BOOT - SLAVE 456 */ 457 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 458 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 459 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 460 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 461 #endif 462 463 /* 464 * eSPI - Enhanced SPI 465 */ 466 467 /* 468 * General PCI 469 * Memory space is mapped 1-1, but I/O space must start from 0. 470 */ 471 #define CONFIG_PCIE1 /* PCIE controller 1 */ 472 #define CONFIG_PCIE2 /* PCIE controller 2 */ 473 #define CONFIG_PCIE3 /* PCIE controller 3 */ 474 #define CONFIG_PCIE4 /* PCIE controller 4 */ 475 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 476 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 477 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 478 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 479 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 480 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 481 482 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 483 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 484 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 485 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 486 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 487 488 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 489 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 490 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 491 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 492 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 493 494 /* controller 4, Base address 203000 */ 495 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 496 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 497 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 498 499 #ifdef CONFIG_PCI 500 #if !defined(CONFIG_DM_PCI) 501 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 502 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 503 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 504 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 506 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 507 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 508 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 509 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 510 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 512 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 513 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 514 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 515 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 516 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 518 #define CONFIG_PCI_INDIRECT_BRIDGE 519 #endif 520 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 521 #endif 522 523 /* Qman/Bman */ 524 #ifndef CONFIG_NOBQFMAN 525 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 526 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 527 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 528 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 529 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 530 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 531 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 532 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 533 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 534 CONFIG_SYS_BMAN_CENA_SIZE) 535 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 536 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 537 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 538 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 539 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 540 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 541 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 542 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 543 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 544 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 545 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 546 CONFIG_SYS_QMAN_CENA_SIZE) 547 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 548 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 549 550 #define CONFIG_SYS_DPAA_FMAN 551 #define CONFIG_SYS_DPAA_PME 552 #define CONFIG_SYS_PMAN 553 #define CONFIG_SYS_DPAA_DCE 554 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 555 #define CONFIG_SYS_INTERLAKEN 556 557 /* Default address of microcode for the Linux Fman driver */ 558 #if defined(CONFIG_SPIFLASH) 559 /* 560 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 561 * env, so we got 0x110000. 562 */ 563 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 564 #elif defined(CONFIG_SDCARD) 565 /* 566 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 567 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 568 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 569 */ 570 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 571 #elif defined(CONFIG_MTD_RAW_NAND) 572 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 573 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 574 /* 575 * Slave has no ucode locally, it can fetch this from remote. When implementing 576 * in two corenet boards, slave's ucode could be stored in master's memory 577 * space, the address can be mapped from slave TLB->slave LAW-> 578 * slave SRIO or PCIE outbound window->master inbound window-> 579 * master LAW->the ucode address in master's memory space. 580 */ 581 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 582 #else 583 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 584 #endif 585 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 586 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 587 #endif /* CONFIG_NOBQFMAN */ 588 589 #ifdef CONFIG_SYS_DPAA_FMAN 590 #define CONFIG_PHY_VITESSE 591 #define CONFIG_PHY_REALTEK 592 #define CONFIG_PHY_TERANETICS 593 #define RGMII_PHY1_ADDR 0x1 594 #define RGMII_PHY2_ADDR 0x2 595 #define FM1_10GEC1_PHY_ADDR 0x3 596 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 597 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 598 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 599 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 600 #endif 601 602 #ifdef CONFIG_FMAN_ENET 603 #define CONFIG_ETHPRIME "FM1@DTSEC3" 604 #endif 605 606 /* 607 * SATA 608 */ 609 #ifdef CONFIG_FSL_SATA_V2 610 #define CONFIG_SYS_SATA_MAX_DEVICE 2 611 #define CONFIG_SATA1 612 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 613 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 614 #define CONFIG_SATA2 615 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 616 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 617 #define CONFIG_LBA48 618 #endif 619 620 /* 621 * USB 622 */ 623 #ifdef CONFIG_USB_EHCI_HCD 624 #define CONFIG_USB_EHCI_FSL 625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 626 #define CONFIG_HAS_FSL_DR_USB 627 #endif 628 629 /* 630 * SDHC 631 */ 632 #ifdef CONFIG_MMC 633 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 634 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 635 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 636 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 637 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 638 #endif 639 640 /* 641 * Dynamic MTD Partition support with mtdparts 642 */ 643 644 /* 645 * Environment 646 */ 647 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 648 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 649 650 /* 651 * Miscellaneous configurable options 652 */ 653 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 654 655 /* 656 * For booting Linux, the board info and command line data 657 * have to be in the first 64 MB of memory, since this is 658 * the maximum mapped by the Linux kernel during initialization. 659 */ 660 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 661 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 662 663 #ifdef CONFIG_CMD_KGDB 664 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 665 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 666 #endif 667 668 /* 669 * Environment Configuration 670 */ 671 #define CONFIG_ROOTPATH "/opt/nfsroot" 672 #define CONFIG_BOOTFILE "uImage" 673 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 674 675 /* default location for tftp and bootm */ 676 #define CONFIG_LOADADDR 1000000 677 #define __USB_PHY_TYPE utmi 678 679 #define CONFIG_EXTRA_ENV_SETTINGS \ 680 "hwconfig=fsl_ddr:" \ 681 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 682 "bank_intlv=auto;" \ 683 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 684 "netdev=eth0\0" \ 685 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 686 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 687 "tftpflash=tftpboot $loadaddr $uboot && " \ 688 "protect off $ubootaddr +$filesize && " \ 689 "erase $ubootaddr +$filesize && " \ 690 "cp.b $loadaddr $ubootaddr $filesize && " \ 691 "protect on $ubootaddr +$filesize && " \ 692 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 693 "consoledev=ttyS0\0" \ 694 "ramdiskaddr=2000000\0" \ 695 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 696 "fdtaddr=1e00000\0" \ 697 "fdtfile=t2080qds/t2080qds.dtb\0" \ 698 "bdev=sda3\0" 699 700 /* 701 * For emulation this causes u-boot to jump to the start of the 702 * proof point app code automatically 703 */ 704 #define CONFIG_PROOF_POINTS \ 705 "setenv bootargs root=/dev/$bdev rw " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "cpu 1 release 0x29000000 - - -;" \ 708 "cpu 2 release 0x29000000 - - -;" \ 709 "cpu 3 release 0x29000000 - - -;" \ 710 "cpu 4 release 0x29000000 - - -;" \ 711 "cpu 5 release 0x29000000 - - -;" \ 712 "cpu 6 release 0x29000000 - - -;" \ 713 "cpu 7 release 0x29000000 - - -;" \ 714 "go 0x29000000" 715 716 #define CONFIG_HVBOOT \ 717 "setenv bootargs config-addr=0x60000000; " \ 718 "bootm 0x01000000 - 0x00f00000" 719 720 #define CONFIG_ALU \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "cpu 1 release 0x01000000 - - -;" \ 724 "cpu 2 release 0x01000000 - - -;" \ 725 "cpu 3 release 0x01000000 - - -;" \ 726 "cpu 4 release 0x01000000 - - -;" \ 727 "cpu 5 release 0x01000000 - - -;" \ 728 "cpu 6 release 0x01000000 - - -;" \ 729 "cpu 7 release 0x01000000 - - -;" \ 730 "go 0x01000000" 731 732 #define CONFIG_LINUX \ 733 "setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "setenv ramdiskaddr 0x02000000;" \ 736 "setenv fdtaddr 0x00c00000;" \ 737 "setenv loadaddr 0x1000000;" \ 738 "bootm $loadaddr $ramdiskaddr $fdtaddr" 739 740 #define CONFIG_HDBOOT \ 741 "setenv bootargs root=/dev/$bdev rw " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_NFSBOOTCOMMAND \ 748 "setenv bootargs root=/dev/nfs rw " \ 749 "nfsroot=$serverip:$rootpath " \ 750 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 751 "console=$consoledev,$baudrate $othbootargs;" \ 752 "tftp $loadaddr $bootfile;" \ 753 "tftp $fdtaddr $fdtfile;" \ 754 "bootm $loadaddr - $fdtaddr" 755 756 #define CONFIG_RAMBOOTCOMMAND \ 757 "setenv bootargs root=/dev/ram rw " \ 758 "console=$consoledev,$baudrate $othbootargs;" \ 759 "tftp $ramdiskaddr $ramdiskfile;" \ 760 "tftp $loadaddr $bootfile;" \ 761 "tftp $fdtaddr $fdtfile;" \ 762 "bootm $loadaddr $ramdiskaddr $fdtaddr" 763 764 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 765 766 #include <asm/fsl_secure_boot.h> 767 768 #endif /* __T208xQDS_H */ 769