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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *
4  * Configuration settings for the Armadeus Project motherboard APF27
5  *
6  * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_ENV_VERSION	10
13 #define CONFIG_BOARD_NAME apf27
14 
15 /*
16  * SoC configurations
17  */
18 #define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
19 #define CONFIG_MACH_TYPE	1698	/* APF27 */
20 
21 /*
22  * Enable the call to miscellaneous platform dependent initialization.
23  */
24 
25 /*
26  * SPL
27  */
28 #define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
29 #define CONFIG_SPL_MAX_SIZE	2048
30 
31 /* NAND boot config */
32 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
34 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800
36 
37 /*
38  * BOOTP options
39  */
40 #define CONFIG_BOOTP_BOOTFILESIZE
41 #define CONFIG_BOOTP_DNS2
42 
43 #define CONFIG_HOSTNAME	"apf27"
44 #define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
45 
46 /*
47  * Memory configurations
48  */
49 #define CONFIG_NR_DRAM_POPULATED 1
50 
51 #define ACFG_SDRAM_MBYTE_SYZE 64
52 
53 #define PHYS_SDRAM_1			0xA0000000
54 #define PHYS_SDRAM_2			0xB0000000
55 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
56 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
57 #define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
58 #define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */
59 
60 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
61 		+ PHYS_SDRAM_1_SIZE - 0x0100000)
62 
63 /*
64  * FLASH organization
65  */
66 #define	ACFG_MONITOR_OFFSET		0x00000000
67 #define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
68 #define	CONFIG_ENV_OVERWRITE
69 #define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
70 #define	CONFIG_FIRMWARE_OFFSET		0x00200000
71 #define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
72 #define	CONFIG_KERNEL_OFFSET		0x00300000
73 #define	CONFIG_ROOTFS_OFFSET		0x00800000
74 
75 /*
76  * U-Boot general configurations
77  */
78 #define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
79 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
80 						/* Boot argument buffer size */
81 
82 /*
83  * Boot Linux
84  */
85 #define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
86 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
87 #define CONFIG_INITRD_TAG		/* send initrd params	*/
88 
89 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
90 
91 #define ACFG_CONSOLE_DEV	ttySMX0
92 #define CONFIG_BOOTCOMMAND	"run ubifsboot"
93 #define CONFIG_SYS_AUTOLOAD	"no"
94 /*
95  * Default load address for user programs and kernel
96  */
97 #define CONFIG_LOADADDR			0xA0000000
98 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
99 
100 /*
101  * Extra Environments
102  */
103 #define CONFIG_EXTRA_ENV_SETTINGS \
104 	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
105 	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
106 	"mtdparts="	 	CONFIG_MTDPARTS_DEFAULT	"\0" \
107 	"partition=nand0,6\0"						\
108 	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
109 	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
110 	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
111 	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
112 	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
113 	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
114 	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
115 	"kernel_addr_r=A0000000\0" \
116 	"check_env=if test -n ${flash_env_version}; "			\
117 		"then env default env_version; "			\
118 		"else env set flash_env_version ${env_version}; env save; "\
119 		"fi; "							\
120 		"if itest ${flash_env_version} < ${env_version}; then " \
121 			"echo \"*** Warning - Environment version"	\
122 			" change suggests: run flash_reset_env; reset\"; "\
123 			"env default flash_reset_env; "\
124 		"fi; \0"						\
125 	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
126 	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
127 		"echo Flash environment variables erased!\0"		\
128 	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
129 		"-u-boot-with-spl.bin\0"				\
130 	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
131 		"nand erase.part u-boot;"		\
132 		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
133 			"then nand lock; nand unlock ${env_addr};"	\
134 				"echo Flashing of uboot succeed;"	\
135 			"else echo Flashing of uboot failed;"		\
136 		"fi; \0"						\
137 	"update_uboot=run download_uboot flash_uboot\0"			\
138 	"download_env=tftpboot ${loadaddr} ${board_name}"		\
139 		"-u-boot-env.txt\0"				\
140 	"flash_env=env import -t ${loadaddr}; env save; \0"		\
141 	"update_env=run download_env flash_env\0"			\
142 	"update_all=run update_env update_uboot\0"			\
143 	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\
144 
145 /*
146  * Serial Driver
147  */
148 #define CONFIG_MXC_UART
149 #define CONFIG_MXC_UART_BASE		UART1_BASE
150 
151 /*
152  * NOR
153  */
154 
155 /*
156  * NAND
157  */
158 
159 #define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
160 #define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
161 #define CONFIG_SYS_MAX_NAND_DEVICE	1
162 
163 #define CONFIG_MXC_NAND_HWECC
164 #define CONFIG_SYS_NAND_LARGEPAGE
165 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
166 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
167 #define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
168 						CONFIG_SYS_NAND_PAGE_SIZE
169 #define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
170 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
171 #define NAND_MAX_CHIPS			1
172 
173 #define CONFIG_FLASH_SHOW_PROGRESS	45
174 #define CONFIG_SYS_NAND_QUIET		1
175 
176 /*
177  * Partitions & Filsystems
178  */
179 
180 /*
181  * Ethernet (on SOC imx FEC)
182  */
183 #define CONFIG_FEC_MXC
184 #define CONFIG_FEC_MXC_PHYADDR		0x1f
185 
186 /*
187  * FPGA
188  */
189 #define CONFIG_FPGA_COUNT		1
190 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
191 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
192 #define CONFIG_SYS_FPGA_CHECK_CTRLC
193 #define CONFIG_SYS_FPGA_CHECK_ERROR
194 
195 /*
196  * Fuses - IIM
197  */
198 #ifdef CONFIG_CMD_IMX_FUSE
199 #define IIM_MAC_BANK		0
200 #define IIM_MAC_ROW		5
201 #define IIM0_SCC_KEY		11
202 #define IIM1_SUID		1
203 #endif
204 
205 /*
206  * I2C
207  */
208 
209 #ifdef CONFIG_CMD_I2C
210 #define CONFIG_SYS_I2C
211 #define CONFIG_SYS_I2C_MXC
212 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
213 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
214 #define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
215 #define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
216 #define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
217 #define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
218 #define CONFIG_SYS_I2C_NOPROBES		{ }
219 
220 #ifdef CONFIG_CMD_EEPROM
221 # define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
222 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
225 #endif /* CONFIG_CMD_EEPROM */
226 #endif /* CONFIG_CMD_I2C */
227 
228 /*
229  * SD/MMC
230  */
231 #ifdef CONFIG_CMD_MMC
232 #define CONFIG_MXC_MCI_REGS_BASE	0x10014000
233 #endif
234 
235 /*
236  * RTC
237  */
238 #ifdef CONFIG_CMD_DATE
239 #define CONFIG_RTC_DS1374
240 #define CONFIG_SYS_RTC_BUS_NUM		0
241 #endif /* CONFIG_CMD_DATE */
242 
243 /*
244  * PLL
245  *
246  *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
247  *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
248  */
249 #define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */
250 
251 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
252 /* micron 64MB */
253 #define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
254 #define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
255 #endif
256 
257 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
258 /* micron 128MB */
259 #define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
260 #define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
261 #endif
262 
263 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
264 /* micron 256MB */
265 #define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
266 #define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
267 #endif
268 
269 #endif /* __CONFIG_H */
270