1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * brtpp1.h 4 * 5 * specific parts for B&R T-Series Motherboard 6 * 7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - 8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 9 */ 10 11 #ifndef __CONFIG_BRPPT1_H__ 12 #define __CONFIG_BRPPT1_H__ 13 14 #include <configs/bur_cfg_common.h> 15 #include <configs/bur_am335x_common.h> 16 /* ------------------------------------------------------------------------- */ 17 /* memory */ 18 #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) 19 #define CONFIG_SYS_BOOTM_LEN SZ_32M 20 21 /* Clock Defines */ 22 #define V_OSCK 26000000 /* Clock output from T2 */ 23 #define V_SCLK (V_OSCK) 24 25 #define CONFIG_POWER_TPS65217 26 27 /* Support both device trees and ATAGs. */ 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 /*#define CONFIG_MACH_TYPE 3589*/ 32 #define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ 33 34 /* 35 * When we have NAND flash we expect to be making use of mtdparts, 36 * both for ease of use in U-Boot and for passing information on to 37 * the Linux kernel. 38 */ 39 40 #ifdef CONFIG_SPL_OS_BOOT 41 #define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 42 43 /* RAW SD card / eMMC */ 44 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 45 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 46 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 47 48 /* NAND */ 49 #ifdef CONFIG_MTD_RAW_NAND 50 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 51 #endif /* CONFIG_MTD_RAW_NAND */ 52 #endif /* CONFIG_SPL_OS_BOOT */ 53 54 #ifdef CONFIG_MTD_RAW_NAND 55 #define CONFIG_SPL_NAND_BASE 56 #define CONFIG_SPL_NAND_DRIVERS 57 #define CONFIG_SPL_NAND_ECC 58 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 59 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 60 #endif /* CONFIG_MTD_RAW_NAND */ 61 62 #ifdef CONFIG_MTD_RAW_NAND 63 #define NANDTGTS \ 64 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 65 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 66 "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ 67 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ 68 "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ 69 "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \ 70 "b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \ 71 "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ 72 "b_tgts_std=usb0 nand net\0" \ 73 "b_tgts_rcy=net usb0 nand\0" \ 74 "b_tgts_pme=usb0 nand net\0" 75 #else 76 #define NANDTGTS "" 77 #endif /* CONFIG_MTD_RAW_NAND */ 78 79 #define MMCSPI_TGTS \ 80 "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ 81 "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \ 82 "b_t30lgcy#0=" \ 83 "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \ 84 "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ 85 "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \ 86 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\ 87 "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ 88 "t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ 89 "b_mode=${b_mode}\0" \ 90 "b_t30lgcy#1=" \ 91 "load ${loaddev}:1 ${loadaddr} zImage && " \ 92 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \ 93 "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \ 94 "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \ 95 "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ 96 "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ 97 "b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \ 98 "b_tgts_rcy=t30lgcy#1 usb0 net\0" \ 99 "b_tgts_pme=net usb0 mmc0 mmc1\0" \ 100 "loaddev=mmc 1\0" 101 102 #ifdef CONFIG_ENV_IS_IN_MMC 103 #define MMCTGTS \ 104 MMCSPI_TGTS \ 105 "cfgscr=mw ${dtbaddr} 0;" \ 106 " mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \ 107 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" 108 #else 109 #define MMCTGTS "" 110 #endif /* CONFIG_MMC */ 111 112 #ifdef CONFIG_SPI 113 #define SPITGTS \ 114 MMCSPI_TGTS \ 115 "cfgscr=mw ${dtbaddr} 0;" \ 116 " sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \ 117 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" 118 #else 119 #define SPITGTS "" 120 #endif /* CONFIG_SPI */ 121 122 #define LOAD_OFFSET(x) 0x8##x 123 124 #ifndef CONFIG_SPL_BUILD 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 BUR_COMMON_ENV \ 127 "verify=no\0" \ 128 "autoload=0\0" \ 129 "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ 130 "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ 131 "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ 132 "loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \ 133 "ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \ 134 "console=ttyO0,115200n8\0" \ 135 "optargs=consoleblank=0 quiet panic=2\0" \ 136 "b_break=0\0" \ 137 "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ 138 "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ 139 MMCTGTS \ 140 SPITGTS \ 141 NANDTGTS \ 142 "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ 143 " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ 144 " else setenv b_tgts ${b_tgts_std}; fi\0" \ 145 "b_default=run b_deftgts; for target in ${b_tgts};"\ 146 " do echo \"### booting ${target} ###\"; run b_${target};" \ 147 " if test ${b_break} = 1; then; exit; fi; done\0" 148 #endif /* !CONFIG_SPL_BUILD*/ 149 150 #ifdef CONFIG_MTD_RAW_NAND 151 /* 152 * GPMC block. We support 1 device and the physical address to 153 * access CS0 at is 0x8000000. 154 */ 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_SYS_NAND_BASE 0x8000000 157 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ 158 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 159 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 161 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 162 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 163 CONFIG_SYS_NAND_PAGE_SIZE) 164 #define CONFIG_SYS_NAND_OOBSIZE 64 165 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 166 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ 167 10, 11, 12, 13, 14, 15, 16, 17, \ 168 18, 19, 20, 21, 22, 23, 24, 25, \ 169 26, 27, 28, 29, 30, 31, 32, 33, \ 170 34, 35, 36, 37, 38, 39, 40, 41, \ 171 42, 43, 44, 45, 46, 47, 48, 49, \ 172 50, 51, 52, 53, 54, 55, 56, 57, } 173 174 #define CONFIG_SYS_NAND_ECCSIZE 512 175 #define CONFIG_SYS_NAND_ECCBYTES 14 176 177 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 178 179 #define CONFIG_NAND_OMAP_GPMC_WSCFG 1 180 #endif /* CONFIG_MTD_RAW_NAND */ 181 182 #if defined(CONFIG_SPI) 183 /* SPI Flash */ 184 /* Environment */ 185 #elif defined(CONFIG_ENV_IS_IN_MMC) 186 #define CONFIG_SYS_MMC_ENV_DEV 1 187 #define CONFIG_SYS_MMC_ENV_PART 2 188 189 #elif defined(CONFIG_ENV_IS_IN_NAND) 190 /* No NAND env support in SPL */ 191 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE 192 #else 193 #error "no storage for Environment defined!" 194 #endif 195 196 #endif /* ! __CONFIG_BRPPT1_H__ */ 197