1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * esd vme8349 U-Boot configuration file 4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 5 * 6 * (C) Copyright 2006-2010 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * reinhard.arlt@esd-electronics.de 10 * Based on the MPC8349EMDS config. 11 */ 12 13 /* 14 * vme8349 board configuration file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_E300 1 /* E300 Family */ 24 25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 27 28 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 29 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 30 #define CONFIG_SYS_MEMTEST_END 0x00100000 31 32 /* 33 * DDR Setup 34 */ 35 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 36 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 37 #define CONFIG_SPD_EEPROM 38 #define SPD_EEPROM_ADDRESS 0x54 39 #define CONFIG_SYS_READ_SPD vme8349_read_spd 40 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 41 42 /* 43 * 32-bit data path mode. 44 * 45 * Please note that using this mode for devices with the real density of 64-bit 46 * effectively reduces the amount of available memory due to the effect of 47 * wrapping around while translating address to row/columns, for example in the 48 * 256MB module the upper 128MB get aliased with contents of the lower 49 * 128MB); normally this define should be used for devices with real 32-bit 50 * data path. 51 */ 52 #undef CONFIG_DDR_32BIT 53 54 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ 55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 56 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 57 #define CONFIG_DDR_2T_TIMING 58 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 59 | DDRCDR_ODT \ 60 | DDRCDR_Q_DRN) 61 /* 0x80080001 */ 62 63 /* 64 * FLASH on the Local Bus 65 */ 66 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 67 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 68 69 70 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 71 72 73 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 74 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 75 76 #undef CONFIG_SYS_FLASH_CHECKSUM 77 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 78 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 79 80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 81 82 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 83 #define CONFIG_SYS_RAMBOOT 84 #else 85 #undef CONFIG_SYS_RAMBOOT 86 #endif 87 88 #define CONFIG_SYS_INIT_RAM_LOCK 1 89 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 90 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 91 92 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 93 GENERATED_GBL_DATA_SIZE) 94 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 95 96 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 97 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 98 99 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 100 101 /* 102 * Serial Port 103 */ 104 #define CONFIG_SYS_NS16550_SERIAL 105 #define CONFIG_SYS_NS16550_REG_SIZE 1 106 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 107 108 #define CONFIG_SYS_BAUDRATE_TABLE \ 109 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 110 111 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 112 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 113 114 /* I2C */ 115 #define CONFIG_SYS_I2C 116 #define CONFIG_SYS_I2C_FSL 117 #define CONFIG_SYS_FSL_I2C_SPEED 400000 118 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 119 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 120 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 121 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 122 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 123 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 124 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 125 126 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 127 128 /* TSEC */ 129 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 130 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 131 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 132 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 133 134 /* 135 * General PCI 136 * Addresses are mapped 1-1. 137 */ 138 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 139 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 140 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 141 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 142 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 143 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 144 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 145 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 146 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 147 148 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 149 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 150 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 151 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 152 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 153 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 154 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 155 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 156 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 157 158 #if defined(CONFIG_PCI) 159 160 #undef CONFIG_EEPRO100 161 #undef CONFIG_TULIP 162 163 #if !defined(CONFIG_PCI_PNP) 164 #define PCI_ENET0_IOADDR 0xFIXME 165 #define PCI_ENET0_MEMADDR 0xFIXME 166 #define PCI_IDSEL_NUMBER 0xFIXME 167 #endif 168 169 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 170 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 171 172 #endif /* CONFIG_PCI */ 173 174 /* 175 * TSEC configuration 176 */ 177 178 #if defined(CONFIG_TSEC_ENET) 179 180 #define CONFIG_GMII /* MII PHY management */ 181 #define CONFIG_TSEC1 182 #define CONFIG_TSEC1_NAME "TSEC0" 183 #define CONFIG_TSEC2 184 #define CONFIG_TSEC2_NAME "TSEC1" 185 #define CONFIG_PHY_M88E1111 186 #define TSEC1_PHY_ADDR 0x08 187 #define TSEC2_PHY_ADDR 0x10 188 #define TSEC1_PHYIDX 0 189 #define TSEC2_PHYIDX 0 190 #define TSEC1_FLAGS TSEC_GIGABIT 191 #define TSEC2_FLAGS TSEC_GIGABIT 192 193 /* Options are: TSEC[0-1] */ 194 #define CONFIG_ETHPRIME "TSEC0" 195 196 #endif /* CONFIG_TSEC_ENET */ 197 198 /* 199 * Environment 200 */ 201 #ifndef CONFIG_SYS_RAMBOOT 202 /* Address and size of Redundant Environment Sector */ 203 #endif 204 205 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 206 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 207 208 /* 209 * BOOTP options 210 */ 211 #define CONFIG_BOOTP_BOOTFILESIZE 212 213 /* 214 * Command line configuration. 215 */ 216 #define CONFIG_SYS_RTC_BUS_NUM 0x01 217 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 218 219 /* Pass Ethernet MAC to VxWorks */ 220 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 221 222 #undef CONFIG_WATCHDOG /* watchdog disabled */ 223 224 /* 225 * Miscellaneous configurable options 226 */ 227 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 228 229 /* 230 * For booting Linux, the board info and command line data 231 * have to be in the first 256 MB of memory, since this is 232 * the maximum mapped by the Linux kernel during initialization. 233 */ 234 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 235 236 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 237 238 /* System IO Config */ 239 #define CONFIG_SYS_SICRH 0 240 #define CONFIG_SYS_SICRL SICRL_LDP_A 241 242 #define CONFIG_SYS_GPIO1_PRELIM 243 #define CONFIG_SYS_GPIO1_DIR 0x00100000 244 #define CONFIG_SYS_GPIO1_DAT 0x00100000 245 246 #define CONFIG_SYS_GPIO2_PRELIM 247 #define CONFIG_SYS_GPIO2_DIR 0x78900000 248 #define CONFIG_SYS_GPIO2_DAT 0x70100000 249 250 #ifdef CONFIG_PCI 251 #define CONFIG_PCI_INDIRECT_BRIDGE 252 #endif 253 254 #if defined(CONFIG_CMD_KGDB) 255 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 256 #endif 257 258 /* 259 * Environment Configuration 260 */ 261 #define CONFIG_ENV_OVERWRITE 262 263 #if defined(CONFIG_TSEC_ENET) 264 #define CONFIG_HAS_ETH0 265 #define CONFIG_HAS_ETH1 266 #endif 267 268 #define CONFIG_HOSTNAME "VME8349" 269 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 270 #define CONFIG_BOOTFILE "uImage" 271 272 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 273 274 #define CONFIG_EXTRA_ENV_SETTINGS \ 275 "netdev=eth0\0" \ 276 "hostname=vme8349\0" \ 277 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 278 "nfsroot=${serverip}:${rootpath}\0" \ 279 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 280 "addip=setenv bootargs ${bootargs} " \ 281 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 282 ":${hostname}:${netdev}:off panic=1\0" \ 283 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 284 "flash_nfs=run nfsargs addip addtty;" \ 285 "bootm ${kernel_addr}\0" \ 286 "flash_self=run ramargs addip addtty;" \ 287 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 288 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 289 "bootm\0" \ 290 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 291 "update=protect off fff00000 fff3ffff; " \ 292 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 293 "upd=run load update\0" \ 294 "fdtaddr=780000\0" \ 295 "fdtfile=vme8349.dtb\0" \ 296 "" 297 298 #define CONFIG_NFSBOOTCOMMAND \ 299 "setenv bootargs root=/dev/nfs rw " \ 300 "nfsroot=$serverip:$rootpath " \ 301 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 302 "$netdev:off " \ 303 "console=$consoledev,$baudrate $othbootargs;" \ 304 "tftp $loadaddr $bootfile;" \ 305 "tftp $fdtaddr $fdtfile;" \ 306 "bootm $loadaddr - $fdtaddr" 307 308 #define CONFIG_RAMBOOTCOMMAND \ 309 "setenv bootargs root=/dev/ram rw " \ 310 "console=$consoledev,$baudrate $othbootargs;" \ 311 "tftp $ramdiskaddr $ramdiskfile;" \ 312 "tftp $loadaddr $bootfile;" \ 313 "tftp $fdtaddr $fdtfile;" \ 314 "bootm $loadaddr $ramdiskaddr $fdtaddr" 315 316 #define CONFIG_BOOTCOMMAND "run flash_self" 317 318 #ifndef __ASSEMBLY__ 319 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 320 unsigned char *buffer, int len); 321 #endif 322 323 #endif /* __CONFIG_H */ 324