1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * (C) Copyright 2009 8 * Stefan Roese, DENX Software Engineering, sr@denx.de. 9 * 10 * (C) Copyright 2011-2012 11 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com 12 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 13 */ 14 15 /* 16 * for linking errors see 17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html 18 */ 19 20 #ifndef _CONFIG_KM_KIRKWOOD_H 21 #define _CONFIG_KM_KIRKWOOD_H 22 23 /* KM_KIRKWOOD */ 24 #if defined(CONFIG_KM_KIRKWOOD) 25 #define CONFIG_HOSTNAME "km_kirkwood" 26 #define CONFIG_KM_DISABLE_PCIE 27 28 /* KM_KIRKWOOD_PCI */ 29 #elif defined(CONFIG_KM_KIRKWOOD_PCI) 30 #define CONFIG_HOSTNAME "km_kirkwood_pci" 31 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 32 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 33 34 /* KM_KIRKWOOD_128M16 */ 35 #elif defined(CONFIG_KM_KIRKWOOD_128M16) 36 #define CONFIG_HOSTNAME "km_kirkwood_128m16" 37 #undef CONFIG_SYS_KWD_CONFIG 38 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 39 #define CONFIG_KM_DISABLE_PCIE 40 41 /* KM_NUSA / KM_SUGP1 */ 42 #elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) 43 44 # if defined(CONFIG_KM_NUSA) 45 #define CONFIG_HOSTNAME "kmnusa" 46 # elif defined(CONFIG_KM_SUGP1) 47 #define CONFIG_HOSTNAME "kmsugp1" 48 #define KM_PCIE_RESET_MPP7 49 #endif 50 51 #undef CONFIG_SYS_KWD_CONFIG 52 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 53 54 /* KM_MGCOGE3UN */ 55 #elif defined(CONFIG_KM_MGCOGE3UN) 56 #define CONFIG_HOSTNAME "mgcoge3un" 57 #undef CONFIG_SYS_KWD_CONFIG 58 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg 59 #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" 60 #define CONFIG_KM_DISABLE_PCIE 61 62 /* KMCOGE5UN */ 63 #elif defined(CONFIG_KM_COGE5UN) 64 #undef CONFIG_SYS_KWD_CONFIG 65 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg 66 #define CONFIG_HOSTNAME "kmcoge5un" 67 #define CONFIG_KM_DISABLE_PCIE 68 69 /* KM_SUV31 */ 70 #elif defined(CONFIG_KM_SUV31) 71 #define CONFIG_HOSTNAME "kmsuv31" 72 #undef CONFIG_SYS_KWD_CONFIG 73 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 74 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 75 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 76 #else 77 #error ("Board unsupported") 78 #endif 79 80 /* include common defines/options for all arm based Keymile boards */ 81 #include "km/km_arm.h" 82 83 #if defined(CONFIG_KM_PIGGY4_88E6352) 84 /* 85 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via 86 * an Marvell 88E6352 simple switch. 87 * In this case we have to change the default settings for the etherent mac. 88 * There is NO ethernet phy. The ARM and Switch are conencted directly over 89 * RGMII in MAC-MAC mode 90 * In this case 1GBit full duplex and autoneg off 91 */ 92 #define PORT_SERIAL_CONTROL_VALUE ( \ 93 MVGBE_FORCE_LINK_PASS | \ 94 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 95 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 96 MVGBE_ADV_NO_FLOW_CTRL | \ 97 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 98 MVGBE_FORCE_BP_MODE_NO_JAM | \ 99 (1 << 9) /* Reserved bit has to be 1 */ | \ 100 MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 101 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 102 MVGBE_DTE_ADV_0 | \ 103 MVGBE_MIIPHY_MAC_MODE | \ 104 MVGBE_AUTO_NEG_NO_CHANGE | \ 105 MVGBE_MAX_RX_PACKET_1552BYTE | \ 106 MVGBE_CLR_EXT_LOOPBACK | \ 107 MVGBE_SET_FULL_DUPLEX_MODE | \ 108 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 109 MVGBE_SET_GMII_SPEED_TO_1000 |\ 110 MVGBE_SET_MII_SPEED_TO_100) 111 112 #endif 113 114 #ifdef CONFIG_KM_PIGGY4_88E6061 115 /* 116 * Some keymile boards like mgcoge3un have their PIGGY4 connected via 117 * an Marvell 88E6061 simple switch. 118 * In this case we have to change the default settings for the 119 * ethernet phy connected to the kirkwood. 120 * In this case 100MB full duplex and autoneg off 121 */ 122 #define PORT_SERIAL_CONTROL_VALUE ( \ 123 MVGBE_FORCE_LINK_PASS | \ 124 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 125 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 126 MVGBE_ADV_NO_FLOW_CTRL | \ 127 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 128 MVGBE_FORCE_BP_MODE_NO_JAM | \ 129 (1 << 9) /* Reserved bit has to be 1 */ | \ 130 MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 131 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 132 MVGBE_DTE_ADV_0 | \ 133 MVGBE_MIIPHY_MAC_MODE | \ 134 MVGBE_AUTO_NEG_NO_CHANGE | \ 135 MVGBE_MAX_RX_PACKET_1552BYTE | \ 136 MVGBE_CLR_EXT_LOOPBACK | \ 137 MVGBE_SET_FULL_DUPLEX_MODE | \ 138 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 139 MVGBE_SET_GMII_SPEED_TO_10_100 |\ 140 MVGBE_SET_MII_SPEED_TO_100) 141 #endif 142 143 #ifdef CONFIG_KM_DISABLE_PCIE 144 #undef CONFIG_KIRKWOOD_PCIE_INIT 145 #endif 146 147 #endif /* _CONFIG_KM_KIRKWOOD */ 148